EP7211 Datasheet, PDF (9/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
LIST OF TABLES
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 3-10.
Table 3-11.
Table 3-12.
Table 3-13.
Table 3-14.
Table 3-15.
Table 3-16.
Table 3-17.
Table 3-18.
Table 4-1.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 5-10.
Table 5-11.
Table 5-12.
Table 5-13.
Table 5-14.
Table 5-15.
Table 5-16.
Table 5-17.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 7-1.
Table 7-2.
Table 7-3.
SSI/Codec/MCP Pin Multiplexing.................................................................................................... 18
256-Ball PBGA Ball Listing ............................................................................................................ 20
PBGA Balls to Connect to Ground (V_SS) ........................................................................................ 23
208-Pin LQFP Numeric Pin Listing ................................................................................................. 24
JTAG Pin Ordering for 208-Pin LQFP Package ............................................................................. 28
Interrupt Allocation in First Interrupt Register ................................................................................. 35
Interrupt Allocation in Second Interrupt Register ............................................................................ 36
Interrupt Allocation in Third Interrupt Register ................................................................................ 36
External Interrupt Source Latencies................................................................................................ 38
Boot Options ................................................................................................................................... 40
Chip Select Address Ranges After Boot From On-Chip Boot ROM ............................................... 40
CL-PS6700 Memory Map ............................................................................................................... 41
Space Field Decoding ..................................................................................................................... 42
Physical to DRAM Address Mapping .............................................................................................. 45
DRAM Address Mapping When Connected to an External 32-Bit DRAM Memory System ........... 46
DRAM Address Mapping for a 16-Bit-Wide DRAM Memory System.............................................. 47
Serial Interface Options .................................................................................................................. 48
Serial-Pin Assignments................................................................................................................... 48
ADC Interface Operation Frequencies............................................................................................ 57
Peripheral Status in Different Power Management States .............................................................. 67
Effect of Endianness on Read Operations...................................................................................... 73
Effect of Endianness on Write Operations ...................................................................................... 73
Instructions Supported in JTAG Mode ............................................................................................ 75
EP7211 Memory Map ..................................................................................................................... 77
CL-PS7111-Compatible................................................................................................................... 79
Internal I/O Memory Locations (EP7211 Only) ............................................................................... 81
Port Byte Addresses in Big Endian Mode ....................................................................................... 81
Values of the Bus Width Field ......................................................................................................... 97
Values of the Wait State Field at 13 MHz and 18 MHz ................................................................... 98
Values of the Wait State Field at 36 MHz........................................................................................ 98
LED Flash Rates........................................................................................................................... 101
LED Duty Ratio ............................................................................................................................. 101
Sense of PWM control lines.......................................................................................................... 102
UART Bit Rates Running from the PLL Clock............................................................................... 104
UART Bit Rates Running from an External 13.0 MHz Clock ........................................................ 104
Grey Scale Value to Color Mapping.............................................................................................. 107
MCP Control Register ................................................................................................................... 117
MCP Data Register 0 .................................................................................................................... 120
MCP Data Register 1 .................................................................................................................... 121
MCP Data Register 2 .................................................................................................................... 123
MCP Control, Data and Status Register Locations ....................................................................... 128
DC Characteristics ........................................................................................................................ 130
AC Timing Characteristics ............................................................................................................ 132
Timing Characteristics .................................................................................................................. 133
I/O Buffer Output Characteristics .................................................................................................. 147
EP7211 Hardware Test Modes ..................................................................................................... 148
Oscillator and PLL Test Mode Signals .......................................................................................... 149
Software Selectable Test Functionality ......................................................................................... 150
DS352PP3
9
JUL 2001