EP7211 Datasheet, PDF (68/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
CPU intervention is needed once its rate and duty ratio have been configured (via the LEDFLSH
register). The LED flash rate period can be programmed for 1, 2, 3, or 4 seconds. The duty ratio can
be programmed such that the mark portion can be 1/16, 2/16, 3/16, …, 16/16 of the full cycle. The
external pin can provide up to 4 mA of drive current.
3.14 Two PWM Interfaces
Two Pulse Width Modulator (PWM) duty ratio clock outputs are provided by the EP7211. When the
device is operating from the internal PLL, this will run at a frequency of 96 kHz. These signals are
intended for use as drives for external DC-to-DC converters in the Power Supply Unit (PSU)
subsystem. External input pins that would normally be connected to the output from comparators
monitoring the external DC-to-DC converter output are also used to enable these clocks. These are
the FB[0:1] pins. The duty ratio (and hence PWMs on time) can be programmed from 1 in 16 to 15
in 16. The sense of the PWM drive signal (active high or low) is determined by latching the state of
this drive signal during power on reset (i.e., a pull-up on the drive signal will result in a active low
drive output, and visa versa). This allows either positive or negative voltages to be generated by the
external DC-to-DC converter. PWMs are disabled by writing zeros into the drive ratio fields in the
PMPCON Pump Control register.
NOTE: To maximize power savings, the drive ratio fields should be used to disable the PWMs, instead of the
FB pins. The clocks that source the PWMs are disabled when the drive ratio fields are zeroed.
3.15 State Control
The EP7211 supports the following Power Management States: Standby, Idle, and Operating.
In the description below, the RUN/CLKEN pin can be used either for the RUN functionality, or the
CLKEN functionality to allow an external oscillator to be disabled in the 13 MHz mode. Either RUN
or CLKEN functionality can be selected according to the state of the CLKENSL bit in the
SYSCON2 register.
The Standby State equates to the system being switched "off" (i.e., no display, and the main oscillator
is shut down). When the 18.432–73.728 MHz mode is selected, the PLL will be shut down. In the 13
MHz mode, if the CLKENSL bit is set low, then the CLKEN signal will be forced low and can, if
required, be used to disable an external oscillator.
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Functional Description
DS352PP3
JUL 2001