EP7211 Datasheet, PDF (46/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
essential that the software monitor the appropriate status registers within the CL-PS6700s to ensure
that there are no pending posted bus transactions before the Standby State is entered. Failure to do
this will result in incomplete PC Card accesses.
3.7 DRAM Controller with EDO Support
The DRAM controller in the EP7211 provides all the connections to directly interface to up to two
banks of (EDO) DRAM, and the width of the memory interface is programmable to 16-bit or 32-bit.
Both banks have to be of the same width. The 16/32-bit DRAM width selection is made based on
Bit 2 of the SYSCON2 register. Each of the two banks supported can be up to 256 Mbytes in size.
Two RAS lines and four CAS lines are provided, with one CAS line per byte lane. The DRAM
controller does not support device size programmability. Therefore, if two banks are implemented
and DRAM devices are used that would create a bank smaller than 256 Mbytes, then this would lead
to a segmented memory map. Each segmented bank will be separated by 256 Mbytes. Segments that
are smaller than the bank size will repeat within the bank. Table 3-9. Physical to DRAM Address
Mapping shows the mapping of the physical address to DRAM row and column addresses. This
mapping has been organized to support any DRAM device size from 4 Mbit to 1 Gbit with a square
row and column configuration (i.e., the number of column addresses is equal to the number of row
addresses). If a non-square DRAM is used, further fragmentation of the memory map will occur,
however the smallest contiguous segment will always be 1 Mbyte. With proper mapping of
pages/sections by the MMU, one can create contiguous memory blocks.
On boot-up, the DRAM controller is configured for operation with an 18.432 MHz internal bus
speed, and therefore, can support either fast page mode or EDO DRAM. In this case, the read data
from the DRAM is latched within the EP7211 during the high phase of the NCAS output strobes.
The DRAM must not have an access time greater than 70 ns in order to meet the 18 MHz timing
requirements. When the internal bus is operating at 36.864 MHz (i.e., for CPU clock frequencies of
36.864, 49.152, or 73.728 MHz), the DRAM controller will only operate with EDO DRAM. When
operating at 36 MHz, the EDO DRAM must not have an access time greater than 50 ns. The DRAM
cycle timings are adjusted to take advantage of the additional performance available from fast EDO
DRAM. In EDO mode, the EP7211 design relies on the DRAM data being driven to be available on
the external data bus during the entire high phase of the NCAS signal so that it can be latched towards
the end of the cycle. In Fast Page mode, the data should be latched at the rising edge of NCAS. It is
not possible to use the EP7211 with fast page mode DRAM at operating frequencies of 36 MHz or
higher.
The DRAM controller breaks all sequential access, so that the minimum page sizes defined can be
supported. All of the possible page sizes are multiples of the minimum page size, so by breaking up
accesses on minimum page sizes by default, all accesses crossing larger page boundaries are broken
up.
NOTE: This bit will be generated by the DRAM controller.
An example of the DRAM connections for a typical system can be found in Figure 3-13. A
Maximum EP7211 Based System.
46
Functional Description
DS352PP3
JUL 2001