EP7211 Datasheet, PDF (130/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
user must clear set status bits before enabling the MCP. Note that writes to reserved bits are ignored
and reads return zeros.
Address: 0x 8000 2018
MCP Status Register: MCSR
Bit 31 30 29 28 27 26 25 24 23 22
Reserved
Reset 0
0
0
0
0
0
0
0
0
0
Read/Write &
Read-Only
21 20 19 18 17 16
0
0
0
0
0
0
Bit 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCE ACE CRC CWC TNE TNF ANE ANF TRO TTU ARO ATU TRS TTS ARS ATS
Reset 0
0
0
0
0
1
0
1
?
?
?
?
0
0
0
0
Figure 5-4. MCP Status Register: MCSR
Table 5-17. MCP Control, Data and Status Register Locations
Bit
Name
Description
0
ATS
Audio Transmit FIFO Service Request Flag (read-only)
0 — Audio transmit FIFO is more than half full (five or more entries filled) or MCP disabled
1 — Audio transmit FIFO is half full or less (four or fewer entries filled) and MCP operation is
enabled, interrupt request signaled if not masked
(if ATM = 1)
1
ARS
Audio Receive FIFO Service Request (read-only)
0 — Audio receive FIFO is less than half full (five or fewer entries filled) or MCP disabled
1 — Audio receive FIFO is half full or more (six or more entries filled) and MCP operation is
enabled, interrupt request signaled if not masked (if ARM = 1)
2
TTS
Telecom Transmit FIFO Service Request Flag (read-only)
0 — Telecom transmit FIFO is more than half full or less (four or fewer entries filled) or MCP
disabled.
1 — Telecom transmit FIFO is half full or less (four or fewer entries filled) and MCP operation is
enabled, interrupt request signaled if not masked
(if TTM = 1)
3
TRS
0 — Telecom receive FIFO is less than half full (five or fewer entries filled) or MCP disabled.
1 — Telecom receive FIFO is half full or more (six or more entries filled) and MCP operation is
enabled, interrupt request signalled if not masked (if TRM = 1)
4
ATU
Audio Transmit FIFO Underrun
0 — Audio transmit FIFO has not experienced an underrun
1 — Audio transmit logic attempted to fetch data from transmit FIFO while it was empty, request
interrupt
5
ARO Audio Receive FIFO Overrun
0 — Audio receive FIFO has not experienced an overrun
1 — Audio receive logic attempted to place data into receive FIFO while it was full, request
interrupt
130
Register Descriptions
DS352PP3
JUL 2001