EP7211 Datasheet, PDF (16/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Function
Signal
Name
NMEDCHG/
BROM
Interrupts
NEXTFIQ
EINT3
NEINT[1–2]
NPWRFL
Power
Management
BATOK
NEXTPWR
NBATCHG
NPOR
RUN/CLKEN
State Control
WAKEUP
NURESET
MCP, Codec or
SSI2
Interface
(See Note)
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
Signal
Description
I
Media changed input; active low, deglitched — it is used as a general purpose
FIQ interrupt during normal operation. It is also used on power up to configure
the processor to either boot from the internal Boot ROM, or from external
memory. When low, the chip will boot from the internal Boot ROM.
I
External active low fast interrupt request input
I
External active high interrupt request input
I
Two general purpose, active low interrupt inputs
I
Power fail input; active low deglitched input to force system into the Standby
State
I
Main battery OK input; falling edge generates a FIQ, a low level in the Standby
State inhibits system start up; deglitched input
I
External power sense; must be driven low if the system is powered by an
external source
I
New battery sense; driven low if battery voltage falls below the "no-battery"
threshold; it is a deglitched input
I
Power-on reset input; active low input completely resets the entire system;
must be held active for at least two clock cycles to be detected cleanly
This pin is programmed to either output the RUN signal or the CLKEN signal.
The CLKENSL bit is used to configure this pin. When RUN is selected, the pin
will be high when the system is active or idle, low while in the Standby State.
When CLKEN is selected, the pin will only be driven low when in the Standby
State.
I
Wake up deglitched input signal; rising edge forces system into the Operating
State; active after a power-on reset
I
User reset input; active low deglitched input from user reset button.
This pin is also latched upon the rising edge of NPOR and read along with the
input pins NTEST[0–1] to force the device into special test modes.
I/O
MCP/Codec/SSI2 clock signal
I/O
MCP/Codec/SSI2 serial data output frame/synchronization pulse output
O
MCP/Codec/SSI2 serial data output
I
MCP/Codec/SSI2 serial data input
I/O
SSI2 serial data input frame/synchronization pulse
16
Pin Information
DS352PP3
JUL 2001