EP7211 Datasheet, PDF (82/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Address
0x8000.0580
0x8000.05C0
0x8000.0600
0x8000.0640
0x8000.0680
0x8000.06C0
0x8000.0700
0x8000.0740
0x8000.0780
0x8000.07C0
0x8000.0800
0x8000.0840
0x8000.0880–
0x8000.0FFF
0x8000.1000
0x8000.1100
0x8000.1140
0x8000.1240
0x8000.1280
0x8000.12C0–
0x8000.147F
0x8000.1480
0x8000.14C0
0x8000.1500
0x8000.1600
0x8000.16C0
0x8000.1700
0x8000.1800
0x8000.1840–
0x8000.1FFF
Name
PALMSW
STFCLR
BLEOI
MCEOI
TEOI
TC1EOI
TC2EOI
RTCEOI
UMSEOI
COEOI
HALT
STDBY
Reserved
Table 5-1. CL-PS7111-Compatible (cont.)
Default
0
RD/WR
RW
—
WR
—
WR
—
WR
—
WR
—
WR
—
WR
—
WR
—
WR
—
WR
—
WR
—
WR
Size
32
—
—
—
—
—
—
—
—
—
—
—
Comments
Most significant 32-bit word of LCD palette reg-
ister
Write to clear all start up reason flags
Write to clear battery low interrupt
Write to clear media changed interrupt
Write to clear tick and watchdog interrupt
Write to clear TC1 interrupt
Write to clear TC2 interrupt
Write to clear RTC match interrupt
Write to clear UART modem status changed
interrupt
Write to clear CODEC sound interrupt
Write to enter the Idle State
Write to enter the Standby State
Write will have no effect, read is undefined
FBADDR
C
SYSCON2
0
SYSFLG2
0
INTSR2
0
INTMR2
0
Reserved
RW
4
LCD frame buffer start address
RW
16
System control register 2
RD
16
System status register 2
RD
24
Interrupt status register 2
RW
16
Interrupt mask register 2
Write will have no effect, read is undefined
UARTDR2
0
UBLCR2
0
SS2DR
0
SRXEOF
—
SS2POP
—
KBDEOI
—
Reserved
—
Reserved
—
RW
8W/11R UART2 Data Register
RW
32
UART2 bit rate and line control register
RW
16
Master/slave SSI2 data Register
WR
—
Write to clear RX FIFO overflow flag
WR
—
Write to pop SSI2 residual byte into RX FIFO
WR
—
Write to clear keyboard interrupt
WR
—
Do not write to this location. A write will cause
the processor to go into an unsupported power
savings state.
Write will have no effect, read is undefined
82
Register Descriptions
DS352PP3
JUL 2001