EP7211 Datasheet, PDF (108/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
13:18
19:24
25:29
30
31
Description
Line length: The line length field is a 6-bit field that sets the number of pixels in one complete line. This
field is calculated from the formula:
line length = (No. pixels in line / 16) – 1
e.g., for 640 x 240 LCD Line length = (640 / 16) – 1 = 39 or 0x27 hex.
The minimum value that can be programmed into this register is a 1 (i.e., 0 is not a legal value).
Pixel prescale: The pixel prescale field is a 6-bit field that sets the pixel rate prescale. The pixel rate is
always derived from a 36.864 MHz clock and is calculated from the formula:
Pixel rate (MHz) = 36.864 / (Pixel prescale + 1)
When the EP7211 is operating at 13 MHz, pixel rate is given by the formula:
Pixel rate (MHz) = 13 / (Pixel prescale + 1)
The pixel prescale value can be expressed in terms of the LCD size by the formula:
When the EP7211 is operating @ 18.432 MHz:
Pixel prescale = (36864000 / (Refresh Rate *Total pixels in display)) – 1
When the EP7211 is operating @ 13 MHz:
Pixel prescale = (13000000 / (Refresh Rate * Total pixels in display)) – 1
Refresh Rate is the screen refresh frequency (70 Hz to avoid flicker)
The value should be rounded down to the nearest whole number and zero is illegal and will result in no
pixel clock.
EXAMPLE: For a system being operated in the 18.432–73.728 MHz mode, with a 640 x 240
screen size, and 70 Hz screen refresh rate desired, the LCD Pixel prescale equals
36.864E6/(70 * 640x240) – 1 = 2.428
Rounding 2.428 down to the nearest whole number equals 2.
This gives an actual pixel rate of 36.864E6 / 2+1 = 12.288 MHz
Which gives an actual refresh frequency of 12.288E6/(640x240) = 80 Hz.
NOTE: As the CL2 low pulse time is doubled after every CL1 high pulse this refresh frequency is only an
approximation, the accurate formula is 12.288E6/((640x240)+120) = 79.937 Hz.
AC prescale: The AC prescale field is a 5-bit number that sets the LCD AC bias frequency. This frequency
is the required AC bias frequency for a given manufacturer’s LCD plate. This frequency is derived from the
frequency of the line clock (CL1). The m signal will toggle after n+1 counts of the line clock (CL1) where n
is the number programmed into the AC prescale field. This number must be chosen to match the manufac-
turer’s recommendation. This is normally 13, but must not be exactly divisible by the number of lines in the
display.
GSEN: Grey scale enable bit. Setting this bit enables grey scale output to the LCD. When this bit is cleared
each bit in the video map directly corresponds to a pixel in the display.
GSMD: Grey scale mode bit. Clearing this bit sets the controller to 2-bits per pixel (4 grey scales), setting it
sets it to 4 bits per pixel (16 grey scales). This bit has no effect if GSEN is cleared.
108
Register Descriptions
DS352PP3
JUL 2001