EP7211 Datasheet, PDF (116/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
calculated using the equation below, where ASD is the decimal equivalent of the binary value
programmed within the bit-field. Note that ASD must be programmed with a value of 6 or larger.
Unpredictable results occur for ASD values smaller than 6. As mentioned elsewhere, the sample
frequency is derived from the equation:
Sample Rate = (MCP’s serial clock frequency) / (32 x ASD)
Using the MCP clock of 9.216 MHz, and an ASD value of 13, a nominal audio codec sample
frequency of 22.05 kHz is achieved within an error of ±0.5%. Although the existing MCP design
includes a provisional input from an external clock and it can be programmed to accept an external
clock, this feature is not enabled in the EP7211.
5.16.1.2 Telecom Sample Rate Divisor (TSD)
The 7-bit telecom sample rate divisor (TSD) bit field is used to synchronize the MCP with the sample
rate of the telecom codec. The telecom sample rate clock is required for the same reason and works
exactly like the audio sample rate clock, except for one minor difference. The valid TSD values range
from 16 to 127 (instead of 6), allowing a total of 112 different audio sample rates to be selected,
ranging from a minimum of 2.953 K samples per second to a maximum of 23.44 K samples per
second.
The resulting telecom sample clock rate, given a specific TSD value can be calculated using the
equation below, where TSD is the decimal equivalent of the binary value programmed within the bit-
field. Although (e.g., in the UCB1100 Philips telecom codec), the telecom divisor can be
programmed with values in the range 6−127, note that TSD must be programmed with a value of 16
or larger. Unpredictable results occur for TSD values smaller than 16. As mentioned elsewhere, the
sample frequency is derived from the equation:
Sample Rate = (MCP’s serial clock frequency) / (32 x TSD)
Using a TSD modulus of 40 and the MCP’s serial clock at 9.216 MHz, the exact nominal Telecom
Sample Frequency of 7.2 kHz is achieved.
5.16.1.3 Multimedia Communications Port Enable (MCE)
The MCP enable (MCE) bit is used to enable and disable all MCP operation.
When the MCP is disabled, all of its clocks are powered down to minimize power consumption. Note
that MCE is the only control bit within the MCP that is reset to a known state. It is cleared to zero to
ensure the MCP is disabled following a reset of the device.
When the MCP is enabled, SCLK begins to transition and the start of the first frame is signaled by
driving the SIBSYNC pin high for one SCLK period. The rising-edge of SIBSYNC coincides with
the rising-edge of SCLK. As long as the MCE bit is set, the MCP operates continuously, transmitting
and receiving 128 bit data frames. When the MCE bit is cleared, the MCP is disabled immediately,
causing the current frame which is being transmitted to be terminated. Clearing MCE resets the
MCP’s FIFOs. However MCP data register 3, the control and the status registers are not reset. The
user must ensure these registers are properly reconfigured before re-enabling the MCP.
116
Register Descriptions
DS352PP3
JUL 2001