EP7211 Datasheet, PDF(56/166 Page) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

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EP7211 Datasheet, PDF (56/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

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EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

Subframe

0 1 0 1 0 1 01

SIBSYNC

01 01 01 01 01

01 01

SIBDOUT Ena

Dis

Audio Ena

Counters

3...................3

Samp/Conv

Figure 3-5. Audio Codec Enable Timing

Referring to the Figure 3-5. Audio Codec Enable Timing, âEnaâ within the data frame on

SIBDOUT represents a control register write to the codec to enable the input portion of the audio

codec. The register is updated with the write at the end of subframe 0, and the audio enable signal

within the codec goes high. Both the MCP and codecâs audio sample rate counters then start to

decrement on the next SIBSYNC pulse. In the example, a divisor value of 3 is used, causing the

counter to decrement to zero after 96 (32 x 3 = 96) SIBCLK cycles occur.

If the input portion of the audio codec is enabled when the counter reaches zero, a sample and A/D

conversion is made. The converted value is then placed into the correct field of the codecâs serial

shift register for transmission back to the MCP in the next data frame. If the output portion of the

audio codec is enabled, an audio data value is taken from the received data supplied by the MCP and

is used for a D/A conversion. Data used in the D/A conversion is always taken from the previous

MCP input frame. If no new data is available within the MCPâs audio transmit FIFO since the last

D/A conversion, the same data is used again (causing audio distortion).

Samples and conversions occur twice as shown in Figure 3-5. Audio Codec Enable Timing.

However, while the counter is decrementing for the third time, the CPU disables the audio codec by

issuing another control register write, represented by the âDisâ data frame on SIBDOUT. The

SIBSYNC pulse following the write causes the disable to take effect, and the MCP and codecâs audio

sample rate counters are stopped and reset to their modulus value.

The MCP and the codecâs audio sample rate counters must be enabled coherently, so that

synchronization is achieved between the two. This is accomplished by first programming both the

MCP and codecâs sample rate modulus values, then performing a codec control register write to

enable the audio sampling rate counter within the codec. The MCP automatically decodes a write to

Functional Description

DS352PP3

JUL 2001

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