EP7211 Datasheet, PDF (112/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.12 STFCLR Clear all ‘Start Up Reason’ flags location
ADDRESS: 0x8000.05C0
A write to this location will clear all the ‘Start Up Reason’ flags in the system flags status register
SYSFLG. The ‘Start Up Reason’ flags should first read to determine the reason why the chip was
started (e.g., a new battery was installed). Any value may be written to this location.
5.13 ‘End Of Interrupt’ Locations
These locations are written to after the appropriate interrupt has been serviced. The write is
performed to clear the interrupt status bit, so that other interrupts can be serviced. Any value may be
written to these locations.
5.13.1 BLEOI Battery Low End of Interrupt
ADDRESS: 0x8000.0600
A write to this location will clear the interrupt generated by a low battery (falling edge of BATOK
with NEXTPWR high).
5.13.2 MCEOI Media Changed End of Interrupt
ADDRESS: 0x8000.0640
A write to this location will clear the interrupt generated by a falling edge of the NMEDCHG input
pin.
5.13.3 TEOI Tick End of Interrupt Location
ADDRESS: 0x8000.0680
A write to this location will clear the current pending tick interrupt and watch dog interrupt.
5.13.4 TC1EOI TC1 End of Interrupt Location
ADDRESS: 0x8000.06C0
A write to this location will clear the under flow interrupt generated by TC1.
5.13.5 TC2EOI TC2 End of Interrupt Location
ADDRESS: 0x8000.0700
A write to this location will clear the under flow interrupt generated by TC2.
5.13.6 RTCEOI RTC Match End of Interrupt
ADDRESS: 0x8000.0740
A write to this location will clear the RTC match interrupt
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Register Descriptions
DS352PP3
JUL 2001