EP7211 Datasheet, PDF (59/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
after the read/write bit is received (during the 41st bit of the frame). The value contained within the
addressed register is sent back to the MCP in the same data frame.
Once the codec control register is written with a value to execute a read or write, the operation is
performed every MCP data frame until a new value is written to the register. Thus, continual reads
or writes are made to the addressed codec register until a new read or write operation is configured.
3.8.3 ADC Interface — Master Mode Only SSI1 (Synchronous Serial Interface)
The first synchronous serial interface allows interfacing to the following peripheral devices:
• In the default mode, the device is compatible with the MAXIM MAX148/9 in external clock
mode. Similar SPI or Microwire compatible devices can be connected directly to the EP7211.
• In the extended mode and with negative-edge triggering selected (the ADCCON and
ADCCKNSEN bits are set, respectively, in the SYSCON3 register), this device can be interfaced
to Analog Devices’ AD7811/12 chip using NADCCS as a common RFS/TFS line.
• Other features of the devices, including power management, can be utilized by software and the
use of the GPIO pins.
The clock output frequency is programmable and only active during data transmissions to save
power. There are four output frequencies selectable, which will be slightly different depending
whether the device is operating in a 13 MHz mode or a 18.432 MHz–73.728 MHz mode (see Table
3-14. ADC Interface Operation Frequencies). The required frequency is selected by programming
the corresponding bits 16 and 17 in the SYSCON1 register. The sample clock (SMPCLK) always
runs at twice the frequency of the shift clock (ADCCLK).
Table 3-14. ADC Interface Operation Frequencies
SYSCON1
Bit 17
0
0
1
1
SYSCON1
Bit 16
0
1
0
1
13.0 MHz Operation ADCCLK
Frequency (kHz)
4.2
16.9
67.7
135.4
18.432–73.728 MHz Operation
ADCCLK Frequency (kHz)
4
16
64
128
The output channel is fed by an 8-bit shift register when the ADCCON bit of SYSCON3 is clear.
When ADCCON is set, up to 16 bits of configuration command can be sent, as specified in the
SYNCIO register. The input channel is captured by a 16-bit shift register. The clock and
synchronization pulses are activated by a write to the output shift register. During transfers the
SSIBUSY (synchronous serial interface busy) bit in the system status flags register is set. When the
transfer is complete and valid data is in the 16-bit read shift register, the SSEOTI interrupt is asserted
and the SSIBUSY bit is cleared.
An additional sample clock (SMPCLK) can be enabled independently and is set at twice the transfer
clock frequency.
DS352PP3
JUL 2001
59
Functional Description