EP7211 Datasheet, PDF (73/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
When the PLL mode is selected, the EXPCLK pin becomes an output. This output signal can then
be used to supply a synchronized clock source to external devices (e.g., a CL-PS6700 PC Card
controller device). When in the PLL mode, PE[2] can be used as a GPIO after power-up.
NOTE: After modifying the CLKCTL[1:0] bits, the next instruction should always be a NOP.
3.17.2 External Clock Input (13 MHz)
An external 13 MHz crystal oscillator can be used to drive all of the EP7211. On power-up, if the
device has been strapped to use the external clock, the ARM720T and the address/data buses both
get clocked at 13 MHz. The fixed clock sources to the various peripherals will have different
frequencies than in the PLL mode. In this configuration, the PLL will not be used at all. The clock
signal should be connected to the EXPCLK pin of the EP7211. In this mode, EXPCLK becomes an
input.
If the CLKENSL bit is set low, then pin CLKEN/RUN (an output pin) provides the CLKEN signal
that can be used to start and stop the external 13 MHz clock source (i.e., the oscillator) used to supply
the clock for the EP7211 and the PWM. In this case, when CLKEN is active (high), it can be used
to enable the external 13 MHz clock source, and when low, it can be used to disable it.
When the Standby State is entered in 13 MHz mode, the 13 MHz source is disabled at the EXPCLK
input pin pad until the Standby State is exited. Therefore, the external clock source does not have to
be disabled to be able to disable the clocks internally.
When in the 13 MHz mode, if the CLKENSL bit is set high, then the Standby State is exited
immediately on a wakeup event or an enabled interrupt occurring. If CLKENSL is set low, then the
EP7211 will set CLKEN high after an interrupt or wakeup event occurs, then wait for between 0.125
s and 0.25 s to allow an external oscillator time to stabilize before the clock is enabled through to the
CPU. Only a non-masked interrupt (e.g., realtime clock match), Port A event (corresponding to a
keypress), or WAKEUP signal asserted will wakeup the EP7211 out of the Standby State. The
timing is shown below for the case where CLKENSL is low:
NOTE: When operating at 13 MHz, the CLKCTL[1:0] bits should not be changed from their default value of
‘00’.
CLKEN timing while entering STDBY mode
13 MHz
CLKEN
Figure 3-11. CLKEN Timing Entering the Standby State
DS352PP3
JUL 2001
73
Functional Description