EP7211 Datasheet, PDF (138/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
EXPCLK
NCS[5:0]
NMWE
A[27:0]
WORD
D[31:0]
EXPRDY
Consecutive expansion write cycles with minimum wait states
W_1&6:5
7
W_$':5
7
Bus held
7
7
Write data
7
7
Write data
Figure 6-3. Expansion and ROM Write Timings
NOTES:
1) t_EXWR = 35 ns at 36.864 MHz
70 ns at 18.432 MHz
120 ns at 13.0 MHz
Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving
EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling
edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock
period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY,
but is shown for clarity.
2) Consecutive reads with sequential access enabled are identical except that the sequential access
wait state field is used to determine the number of wait states, and no idle cycles are inserted
between successive non-sequential ROM/expansion cycles. This improves performance so the
SQAEN bit should always be set where possible.
3) Zero wait states for sequential writes is not permitted for memory devices which use NMWE pin, as
this cannot be driven with valid timing under zero wait state conditions.
138
Electrical Specifications
DS352PP3
JUL 2001