EP7211 Datasheet, PDF (97/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
2
12
13
Description
SS2TX: Synchronous serial interface 2 transmit FIFO less than half empty interrupt. This is generated
when TX FIFO contains fewer than 8 byte pairs. This interrupt gets cleared by loading the FIFO with more
data or disabling the TX. One synchronization clock required when disabling the TX side before it takes
effect.
UTXINT2: UART2 transmit FIFO half empty interrupt. The function of this interrupt source depends on
whether the UART2 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART2 bit rate and
line control register), this interrupt will be active when there is no data in the UART2 TX data holding regis-
ter and be cleared by writing to the UART2 data register. If the FIFO is enabled this interrupt will be active
when the UART2 TX FIFO is half or more empty, and is cleared by filling the FIFO to at least half full.
URXINT2: UART2 receive FIFO half full interrupt. The function of this interrupt source depends on whether
the UART2 FIFO is enabled. If the FIFO is disabled this interrupt will be active when there is valid RX data
in the UART2 RX data holding register and be cleared by reading this data. If the FIFO is enabled this
interrupt will be active when the UART2 RX FIFO is half or more full or if the FIFO is non empty and no
more characters have been received for a three character time out period. It is cleared by reading all the
data from the RX FIFO.
5.3.4 INTMR2 Interrupt Mask Register 2
ADDRESS: 0x8000.1280
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
SS2TX
1
SS2RX
0
KBDINT
15
Reserved
14
Reserved
13
URXINT2
12
UTXINT2
11
Reserved
10
Reserved
9
Reserved
8
Reserved
This register is an extension of INTMR1, containing interrupt mask bits for the backward
compatibility with the CL-PS7111. Please refer to INTSR2 for individual bit details.
5.3.5 INTSR3 Interrupt Status Register 3
ADDRESS: 0x8000.2240
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
MCPINT
This register is an extension of INTSR1 and INTSR2 containing status bits for the new features of
the EP7211. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given
below.
Bit
0
Description
MCPINT: MCP interface interrupt. The cause must be determined by reading the MCP status register. It is
mapped to the FIQ interrupt on the ARM720T processor
DS352PP3
JUL 2001
97
Register Descriptions