EP7211 Datasheet, PDF (7/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.6 LEDFLSH Register................................................................................................................................104
5.7 PMPCON Pump Control Register .........................................................................................................105
5.8 CODR — The CODEC Interface Data Register ....................................................................................106
5.9 UART Registers ....................................................................................................................................106
5.9.1 UARTDR1–2 UART1–2 Data Registers ...................................................................................106
5.9.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers...................................................107
5.10 LCD Registers .......................................................................................................................................108
5.10.1 LCDCON — The LCD Control Register ...................................................................................108
5.10.2 PALLSW Least Significant Word — LCD Palette Register....................................................... 110
5.10.3 PALMSW Most Significant Word — LCD Palette Register ....................................................... 110
5.10.4 FBADDR LCD Frame Buffer Start Address .............................................................................. 111
5.11 SSI Register .......................................................................................................................................... 111
5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register ..................................................... 111
5.12 STFCLR Clear all ‘Start Up Reason’ flags location ............................................................................... 113
5.13 ‘End Of Interrupt’ Locations................................................................................................................... 113
5.13.1 BLEOI Battery Low End of Interrupt ......................................................................................... 113
5.13.2 MCEOI Media Changed End of Interrupt ................................................................................. 113
5.13.3 TEOI Tick End of Interrupt Location ......................................................................................... 113
5.13.4 TC1EOI TC1 End of Interrupt Location .................................................................................... 113
5.13.5 TC2EOI TC2 End of Interrupt Location .................................................................................... 113
5.13.6 RTCEOI RTC Match End of Interrupt ....................................................................................... 113
5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt ..................................................... 114
5.13.8 COEOI Codec End of Interrupt Location .................................................................................. 114
5.13.9 KBDEOI Keyboard End of Interrupt Location ........................................................................... 114
5.13.10 SRXEOF End of Interrupt Location .......................................................................................... 114
5.14 State Control Registers ......................................................................................................................... 114
5.14.1 STDBY Enter the Standby State Location ................................................................................ 114
5.14.2 HALT Enter the Idle State Location .......................................................................................... 114
5.15 SS2 Registers ....................................................................................................................................... 115
5.15.1 SS2DR Synchronous Serial Interface 2 Data Register ............................................................ 115
5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte .................................................. 115
5.16 MCP Register Definitions ...................................................................................................................... 115
5.16.1 MCP Control Register .............................................................................................................. 116
5.16.1.1 Audio Sample Rate Divisor (ASD) ........................................................................... 116
5.16.1.2 Telecom Sample Rate Divisor (TSD) ....................................................................... 117
5.16.1.3 Multimedia Communications Port Enable (MCE) ..................................................... 117
5.16.1.4 A/D Sampling Mode (ADM) ...................................................................................... 118
5.16.1.5 MCP Interrupt Generation ........................................................................................ 118
5.16.1.6 Telecom Transmit FIFO Interrupt Mask (TTM) ......................................................... 118
5.16.1.7 Telecom Receive FIFO Interrupt Mask (TRM) ......................................................... 118
5.16.1.8 Audio Transmit FIFO Interrupt Mask (ATM) ............................................................. 119
5.16.1.9 Audio Receive FIFO Interrupt Mask (ARM) ............................................................. 119
5.16.1.10 Loop Back Mode (LBM) ........................................................................................... 119
5.16.2 MCP Data Registers.................................................................................................................121
5.16.2.1 MCP Data Register 0 ...............................................................................................121
5.16.2.2 MCP Data Register 1 ...............................................................................................123
5.16.2.3 MCP Data Register 2 ...............................................................................................125
5.16.3 MCP Status Register ................................................................................................................127
DS352PP3
7
JUL 2001