EP7211 Datasheet, PDF (125/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Address: 0x 8000 2010
MCP Data Register 2: MCDR2
Read/Write
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Erg Address R/W
0
Reset 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ?
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data Value Returned by a Codec Register Read or Write
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Read Access
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Erg Address R/W
R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ?
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data Value to be Written to the Addressed Codec Register
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Write Access
Figure 5-3. MCP Data Register 2: MCDR2
Table 5-16. MCP Data Register 2
Bit
15–0
Name
Codec Register
Read/Write Data
16 R/W
20–17
Codec Register
Read/Write
Address
31–21 —
Description
Codec Register Read/Write Data
Read — If a codec write was last performed, contains data of previous register access, next
frame contains the data which was written. If a codec read was last performed, contains data
from the read register
Write — Used to specify what data to write to the addressed register, ignored for a codec
register read
Read/Write
Read — Returns a zero
Write — Used to control whether the addressed register is read or written
(write = 1, read = 0)
Codec Register Read/Write Address
Read — If a codec write was last performed, contains address of previous register access,
next frame contains the address of the write. If a codec read was last performed, contains
address of the register read
Write — Used to address a register to perform a read or write
Reserved
DS352PP3
JUL 2001
125
Register Descriptions