EP7211 Datasheet, PDF (139/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
DRAM Word Read followed by Page Mode Read (EXPCLK shown for reference only)
EXPCLK
DRA[12:0]
NRAS[1:0]
NCAS[3:0]
D[31:0]
ROW
COL
W_5$6
W_5&
7
W₅₃
ROW
7
COL1 COL2 COLn
7
7
W_&3
W_3&
W_&$6
1
2
n
NMOE
NMWE
WORD/
HALFWORD
WRITE
Figure 6-4. DRAM Read Cycles at 13 MHz and 18.432 MHz
NOTES:
1) t_RC (Read cycle time) = 150 ns max at 18.432 MHz and 230 ns at 13 MHz
2) t_RAS (RAS pulse width) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz
3) t_RP (RAS precharge time) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz
4) t_CAS (CAS pulse width) = 20 ns max at 18.432 MHz and 30 ns at 13 MHz
5) t_CP (CAS precharge in page mode) = 12 ns max at 18.432 MHz and 20 ns at 13 MHz
6) t_PC (Page mode cycle time) = 45 ns min at max at 18.432 MHz and 70 ns at 13 MHz
Word reads shown, for byte reads only one off NCAS[3:0] will be active, NCAS0 for byte 0, etc.
DS352PP3
JUL 2001
139
Electrical Specifications