EP7211 Datasheet, PDF (98/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.3.6 INTMR3 Interrupt Mask Register 3
ADDRESS: 0x8000.2280
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
MCPINT
This register is an extension of INTMR1 and INTMR2, containing interrupt mask bits for the new
features of the EP7211. Please refer to INTSR3 for individual bit details.
5.4 Memory Configuration Registers
5.4.1 MEMCFG1 Memory Configuration Register 1
ADDRESS: 0x8000.0180
31
24
NCS3 configuration
23
16
NCS2 configuration
15
8
NCS1 configuration
7
0
NCS0 configuration
Expansion and ROM space is selected by one of eight chip selects. One of the chip selects (CS6) is
used internally for the on-chip SRAM, and the configuration is hardwired for 32-bit wide, minimum
wait state operation. CS7 is used for the on-chip Boot ROM and the configuration field is hardwired
for 8-bit wide, minimum wait state operation. Data written to the configuration fields for either CS6
or CS7 will be ignored. Two of the chip selects (NCS4 and 5) can be used to access two CL-PS6700
PC CARD controller devices, and when either of these interfaces is enabled, the configuration field
for the appropriate chip select in the MEMCFG2 register is ignored. When the PC CARD1 or 2
control bit in the SYSCON2 register is disabled, then NCS4 and NCS5 are active as normal and can
be programmed using the relevant fields of MEMCFG2, as for the other four chip selects. All of the
six external chip selects are active for 256 Mbytes and the timing and bus transfer width can be
programmed individually. This is accomplished by programming the six byte-width fields contained
in two 32-bit registers, MEMCFG1 and MEMCFG2. All bits in these registers are cleared by a
system reset (except for the CS6 and CS7 configurations).
The memory configuration register 1 is a 32-bit read/write register which sets the configuration of
the four expansion and ROM selects NCS0–NCS3. Each select is configured with a 1-byte field
starting with expansion select 0.
98
Register Descriptions
DS352PP3
JUL 2001