EP7211 Datasheet, PDF (10/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
LIST OF FIGURES
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Figure 3-10.
Figure 3-11.
Figure 3-12.
Figure 3-13.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.
Figure 6-5.
Figure 6-6.
Figure 6-7.
Figure 6-8.
Figure 6-9.
Figure 6-10.
Figure 6-11.
Figure 6-12.
Figure 6-13.
Figure 6-14.
Figure 6-15.
A EP7211–Based System................................................................................................................... 3
208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ...............................................................13
256-Ball Plastic Ball Grid Array Diagram ..........................................................................................14
EP7211 Block Diagram .....................................................................................................................37
Codec Interrupt Timing .....................................................................................................................52
Data Format of MCP Subframe 0 .....................................................................................................55
MCP Packet Organization ................................................................................................................55
Audio Codec Enable Timing .............................................................................................................57
Format for the Audio and Telecom FIFOs.........................................................................................59
SSI2 Port Directions in Slave and Master Mode...............................................................................61
Residual Byte Reading .....................................................................................................................63
Video Buffer Mapping .......................................................................................................................66
State Diagram ...................................................................................................................................72
CLKEN Timing Entering the Standby State.......................................................................................74
CLKEN Timing Leaving the Standby State ......................................................................................75
A Maximum EP7211 Based System .................................................................................................77
MCP Data Register 0: MCDR0 .......................................................................................................122
MCP Data Register 1: MCDR1 .......................................................................................................124
MCP Data Register 2: MCDR2 .......................................................................................................126
MCP Status Register: MCSR .........................................................................................................131
Expansion and ROM Timing ...........................................................................................................137
Expansion and ROM Sequential Read Timings..............................................................................138
Expansion and ROM Write Timings ................................................................................................139
DRAM Read Cycles at 13 MHz and 18.432 MHz ........................................................................... 140
DRAM Read Cycles at 36 MHz ......................................................................................................141
DRAM Write Cycles at 13 MHz and 18 MHz ..................................................................................142
DRAM Write Cycles at 36 MHz.......................................................................................................143
Video Quad Word Read from DRAM at 13 MHz and 18 MHz ........................................................144
Quad Word Read from DRAM at 36 MHz.......................................................................................145
DRAM CAS Before RAS Refresh Cycle at 13 MHz and 18 MHz....................................................146
DRAM CAS Before RAS Refresh Cycle at 36 MHz ........................................................................ 147
LCD Controller Timings...................................................................................................................148
SSI Interface for AD7811/2 .............................................................................................................148
SSI Timing Interface for MAX148/9 ................................................................................................149
SSI2 Interface Timings....................................................................................................................149
10
DS352PP3
JUL 2001