EP7211 Datasheet, PDF (77/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
NOTE: A system can only use one of the following peripheral interfaces at any given time: SSI2, codec, or
MCP.
3.21 Boundary Scan
IEEE 1149.1 compliant JTAG is provided with the EP7211. (It should be noted that a full system
reset, BNRES[0] = ’0’, must be applied to the device initially.)
Table 3-18. Instructions Supported in JTAG Mode
Instruction
BYPASS
IDCODE
SAMPLE/PRELOAD
EXTEST
SCAN_N
Code
1111
1110
0011
0000
0010
The INTEST function will not be supported for the EP7211.
Additional user-defined instructions exist, but these are not relevant to board-level testing. For
further information please refer to the ARM DDI 0087E ARM720T Datasheet Section 8.
As there are additional scan-chains within the ARM720T processor, it is necessary to include a scan-
chain select function — shown as SCAN_N in Table 3-18. Instructions Supported in JTAG
Mode. To select a particular scan chain, this function must be input to the TAP controller, followed
by the 4-bit scan-chain identification code. The identification code for the boundary scan chain is
0011.
Note that it is only necessary to issue the SCAN_N instruction if the device is already in the JTAG
mode. The boundary scan chain is selected as the default on test-logic reset and any of the system
resets.
The contents of the device ID-register for the EP7211 are shown below:
Version
Part number
Manufacturer ID
00001111000011110000111100001111
This is equivalent to 0F0F0F0F Hex. Note this is the ID-code for the ARM720T processor.
DS352PP3
JUL 2001
77
Functional Description