EP7211 Datasheet, PDF (123/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
The following figure shows MCDR1. Note that the transmit and receive telecom FIFOs are cleared
when the device is reset, or by writing a zero to MCE (MCP disabled). Also, note that writes to
reserved bits are ignored and reads return zeros.
Address: 0x 8000 200C
MCP Data Register 1: MCDR1
Read/Write
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bottom of Telecom Receive FIFO
00
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read Access
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Top of Telecom Transmit FIFO
00
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Write Access
Figure 5-2. MCP Data Register 1: MCDR1
Bit
1–0
15–2
31–16
Name
—
Telecom
Data
—
Table 5-15. MCP Data Register 1
Description
Reserved for future enhancements
Read — Data returned, but UCB1100 currently zero fills these two bits
Write — MCP’s transmit logic sends these bits, even though they are ignored by the UCB1100
Transmit/Receive Telecom FIFO Data
Read — Bottom of Telecom Receive FIFO data
Write — Top of Telecom Transmit FIFO data
Reserved
DS352PP3
JUL 2001
123
Register Descriptions