EP7211 Datasheet, PDF (41/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
In the case where KBWEN is low and the INTMR2 bit 0 is low, it will only be possible to wakeup
the device by using the external WAKEUP pin or another enabled interrupt source. The keyboard
interrupt capability allows an OS to use either a polled or interrupt-driven keyboard routine, or a
combination of both.
NOTE: The keyboard interrupt is NOT deglitched.
3.4 Memory and I/O Expansion Interface
Six separate linear memory or expansion segments are decoded by the EP7211, two of which can be
reserved for two PC Card cards, each interfacing to a separate single CL-PS6700 device. Each
segment is 256 Mbytes in size. Two additional segments (i.e., in addition to these six) are dedicated
to the on-chip SRAM and the on-chip ROM. The on-chip ROM space is fully decoded, and the
SRAM space is fully decoded up to the maximum size of the video frame buffer programmed in the
LCDCON register (128 kbytes). Beyond this address range the SRAM space is not fully decoded
(i.e., any accesses beyond 128 kbyte range get wrapped around to within 128 kbyte range). Any of
the six segments can be configured to interface to a conventional SRAM-like interface, and can be
individually programmed to be 8-, 16-, or 32-bits wide, to support page mode access, and to execute
from 1 to 4 wait states for non-sequential accesses and 0 to 3 for burst mode accesses. The zero wait
state sequential access feature is designed to support burst mode ROMs. For writeable memory
devices which use the NMWE pin, zero wait state sequential accesses are not permitted and one wait
state is the minimum which should be programmed in the sequential field of the appropriate
MEMCFG register. Bus cycles can also be extended using the EXPRDY input signal.
Page mode access is accomplished by setting SQAEN = 1, which enables accesses of the form one
random address followed by three sequential addresses, etc., while keeping NCS asserted. These
sequential bursts can be up to four words long before NCS is released to allow DMA and refreshes
to take place. This can significantly improve bus bandwidth to devices such as ROMs which support
page mode. When SQAEN = 0, all accesses to the ROM/SRAM/Flash are by random access without
NCS being de-asserted between accesses. Again NCS is de-asserted after four consecutive accesses
to allow refreshes, etc.
Bits 5 and 6 of the SYSCON2 register independently enable the interfaces to the CL-PS6700 (PC
Card slot drivers). When either of these interfaces are enabled, the corresponding chip select (NCS4
and/or NCS5) becomes dedicated to that CL-PS6700 interface. The state of SYSCON2 Bit 5
determines the function of chip select NCS4 (i.e., CL-PS6700 interface or standard chip select
functionality); Bit 6 controls NCS5 in a similar way. There is no interaction between these bits.
For applications that require a display buffer smaller than 38,400 bytes, the on-chip SRAM can be
used as the frame buffer and no external DRAM needs to be used.
The width of the boot device can be chosen by selecting values of PE[1] and PE[0] during power on
reset. These inputs are latched by the rising edge of NPOR to select the boot option.
DS352PP3
JUL 2001
41
Functional Description