EP7211 Datasheet, PDF (44/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
internal write buffer) then the access will continue on the following two clock cycles. During these
following two clock cycles the upper and lower halves of the word to be read or written will be put
onto the lower 16 bits of the main data bus.
Table 3-8. Space Field Decoding
Space Field Value
00
01
10
11
PC CARD Memory Space
Attribute
I/O
Common memory
CL-PS6700 registers
The ‘ptype’ signal on the CL-PS6700s should be connected to the EP7211’s WRITE output pin.
During PC Card accesses, the polarity of this pin changes and it becomes low to signify a write and
high to signify a read. It is valid with the first half word of the address. During the second half word
of the address it is always forced high to indicate to the CL-PS6700 that the EP7211 has initiated
either the write or read.
The PRDY signals from each of the two CL-PS6700 devices are connected to Port B bits 0 and 1,
respectively. When the PC CARD1 or PC CARD2 control bits in the SYSCON2 register are de-
asserted, these port bits are available for GPIO. When asserted, these port bits are used as the PRDY
signals. When the PRDY signal is de-asserted (i.e., low), it indicates that the CL-PS6700 is busy
accessing its card. If a PC CARD access is attempted while the device is busy, the PRDY signal will
cause the EP7211’s CPU to be stalled. The EP7211’s CPU will have to wait for the card to become
available. DMA transfers to the LCD can still continue in the background during this period of time
(as described below). The EP7211 can access the registers in the CL-PS6700, regardless of the state
of the PRDY signal. If the EP7211 needs to access the PC CARD via the CL-PS6700, it waits until
the PRDY signal is high before initiating a transfer request. Once a request is sent, the PRDY signal
indicates if data is available.
In the case of a PC Card write, writes can be posted to the CL-PS6700 device, with the same timing
as CL-PS6700 internal register writes. Writes will normally be completed by the CL-PS6700 device
independent of the EP7211 processor activity. If a posted write times out, or fails to complete for any
other reason, then the CL-PS6700 will issue an interrupt (i.e., a WR_FAIL interrupt). In the case
where the CL-PS6700 write buffer is already full, the PRDY signal will be de-asserted (i.e., driven
low) and the transaction will be stalled pending an available slot in the buffer. In this case, the
EP7211’s CPU will be stalled until the write can be posted successfully. While the PRDY signal is
de-asserted, the chip select to the CL-PS6700 will be de-asserted and the main bus will be released
so that DMA transfers to the LCD controller can continue in the background.
In the case of a PC Card read, the PRDY signal from the CL-PS6700 will be de-asserted until the
read data is ready. At this point, it will be reasserted and the access will be completed in the same
way as for a register access. In the case of a byte access, only one 16-bit data transfer will be required
to complete the access. While the PRDY signal is de-asserted, the chip select to the CL-PS6700 will
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Functional Description
DS352PP3
JUL 2001