EP7211 Datasheet, PDF (126/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.16.3 MCP Status Register
ADDRESS: 0x8000.2100
The MCP Status Register (MCSR) contains bits which signal FIFO overrun and underrun errors and
FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller.
The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not
empty, when a codec control register read or write is complete, and when the audio or telecom
portion of the codec is enabled (no interrupt generated).
Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags.
Status bits are referred to as “sticky” (once set by hardware, they must be cleared by software).
Writing a one to a sticky status bit clears it, writing a zero has no effect. Read-only flags are set and
cleared by hardware, and writes have no effect. Additionally some bits which cause interrupts have
corresponding mask bits in the control register and are indicated in the section headings below. Note
that the user has the ability to mask all MCP interrupts by clearing the MCP bit within the interrupt
controller mask register INTMR3.
5.16.3.1 Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable interrupt)
The audio transmit FIFO service request flag (ATS) is a read-only bit which is set when the audio
transmit FIFO is nearly empty and requires service to prevent an underrun. ATS is set any time the
audio transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared when it
has five or more entries of valid data. When the ATS bit is set, an interrupt request is made unless
the audio transmit FIFO interrupt request mask (ATM) bit is cleared. After the CPU fills the FIFO
such that four or more locations are filled within the audio transmit FIFO, the ATS flag (and the
service request and/or interrupt) is automatically cleared.
5.16.3.2 Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable interrupt)
The audio receive FIFO service request flag (ARS) is a read-only bit which is set when the audio
receive FIFO is nearly filled and requires service to prevent an overrun. ARS is set any time the audio
receive FIFO has six or more entries of valid data (half full or more), and cleared when it has five or
fewer (less than half full) entries of data. When the ARS bit is set, an interrupt request is made unless
the audio receive FIFO interrupt request mask (ARM) bit is cleared. After six or more entries are
removed from the receive FIFO, the TRS flag (and the service request and/or interrupt) is
automatically cleared.
5.16.3.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable
interrupt)
The telecom transmit FIFO service request flag (TTS) is a read-only bit which is set when the
telecom transmit FIFO is nearly empty and requires service to prevent an underrun. TTS is set any
time the telecom transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared
when it has five or more entries of valid data. When the TTS bit is set, an interrupt request is made
unless the telecom transmit FIFO interrupt request mask (TTM) bit is cleared. After the CPU fills the
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Register Descriptions
DS352PP3
JUL 2001