EP7211 Datasheet, PDF (129/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
1) A register read command is issued to the codec by writing to MCDR2.
2) The read command is sent to the codec via subframe 0.
3) The data value contained within the addressed codec register is loaded into the codec’s serial shift
register during subframe 0 (the 41st bit of the frame).
4) The address and value which was read is returned to the MCP via the same subframe 0.
5) The returned value is latched in MCDR2.
CRC is automatically cleared when MCDR2 is read or written. This bit does not request an interrupt.
5.16.3.15 Audio Codec Enabled Flag (ACE) (read-only, non-interruptible)
The audio codec enabled (ACE) flag indicates when the audio codec input and/or output is enabled.
This in turn indicates that the audio sample rate counter is enabled. This flag is set after the following
sequence occurs:
1) A register write command is issued to Audio Control Register B (register 8), and either bit 14 or
15 is set (aud_in_ena or aud_out_ena) by writing to MCDR2.
2) The write command is sent to the codec via subframe 0.
3) The data value is latched within codec register 8.
4) SIBSYNC is asserted to indicate the start of the next frame.
ACE is automatically cleared using the same sequence, with the exception that bit 14 and 15 are
cleared, disabling both the input and output path of the audio codec. This bit does not request an
interrupt.
5.16.3.16 Telecom Codec Enabled Flag (TCE) (read-only, non-interruptible)
The telecom codec enabled (TCE) flag indicates when the telecom codec input and/or output is
enabled. This in turn indicates that the telecom sample rate counter is enabled. This flag is set after
the following sequence occurs:
1) A register write command is issued to Telecom Control Register B (register 6), and either bit 14
or 15 is set (tel_in_ena or tel_out_ena) by writing to MCDR2.
2) The write command is sent to the codec via subframe 0.
3) The data value is latched within codec register 6.
4) SIBSYNC is asserted to indicate the start of the next frame.
TCE is automatically cleared using the same sequence, with the exception, that bit 14 and 15 are
cleared, disabling both the input and output path of the telecom codec. This bit does not request an
interrupt.
The following figure shows the bit locations corresponding to the status and flag bits within the MCP
status register. MCSR contains a collection of read/write, read-only, interruptible, and non-
interruptible bits (refer to the bit descriptions above). Writes to read-only bits have no effect. The
DS352PP3
JUL 2001
129
Register Descriptions