EP7211 Datasheet, PDF (107/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
14
15
16
17:18
Description
EVENPRT: Even parity bit. Setting this bit sets parity generation and checking to even parity, clearing it
sets odd parity. This bit has no effect if the PRTEN bit is clear.
XSTOP: Extra stop bit. Setting this bit will cause the UART to transmit two stop bits after each data byte,
clearing it will transmit one stop bit after each data byte.
FIFOEN: Set to enable FIFO buffering of RX and TX data. Clear to disable the FIFO (i.e., set its depth to
one byte).
WRDLEN: This two bit field selects the word length according to the table below.
WRDLEN
00
01
10
11
Word Length
5 bits
6 bits
7 bits
8 bits
5.10 LCD Registers
5.10.1 LCDCON — The LCD Control Register
ADDRESS: 0x8000.02C0
31
GSMD
30
GSEN
29:25
AC prescale
24:19
Pixel prescale
18:13
Line length
12:0
Video buffer size
The LCD control register is a 32-bit read/write register that controls the size of the LCD screen and
the operating mode of the LCD controller. Refer to the system description of the LCD controller for
more information on video buffer mapping.
The LCDCON register should only be reprogrammed when LCD controller is disabled.
Bit
0:12
Description
Video buffer size: The video buffer size field is a 13-bit field that sets the total number of bits x 128 (quad
words) in the video display buffer. This is calculated from the formula:
Video buffer size = (Total bits in video buffer / 128) – 1
e.g., for a 640 x 240 LCD and 4-bits per pixel, the size of the video buffer = 640 x 240 x
4 = 614400 bits
Video buffer size field = (614400 / 128) – 1 = 4799 or 0x12BF hex.
The minimum value allowed is 3 for this bit field.
DS352PP3
JUL 2001
107
Register Descriptions