EP7211 Datasheet, PDF (88/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.2.2 SYSCON2 System Control Register 2
ADDRESS: 0x8000.1100
7
SS2RXEN
6
PC CARD2
5
PC CARD1
4
SS2TXEN
3
KBWEN
2
DRAMSZ
1
KBD6
0
SERSEL
15
Reserved
14
BUZFREQ
13
CLKENSL
12
OSTB
11
Reserved
10
Reserved
9
SS2MAEN
8
UART2EN
This register is an extension of SYSCON1, containing additional control for the EP7211, for
compatibility with CL-PS7111. The bits of this second system control register are defined below.
The SYSCON2 register is reset to all 0s on power up.
Bit
0
Description
SERSEL:The only affect of this bit is to select either SSI2 or the codec to interface to the external pins.
See the table below for the selection options.
NOTE: If the MCPSEL bit of SYSCON3 is set, then it overrides the state of the SERSEL bit, and thus the
external pins are connected to the MCP interface.
SERSEL Value
0
1
Selected Serial Device to
External Pins
Master/slave SSI2
Codec
1
KBD6: The state of this bit determines how many of the Port A inputs are OR’ed together to create the
keyboard interrupt. When zero (the reset state), all eight of the Port A inputs will generate a keyboard inter-
rupt. When set high, only Port A bits 0 to 5 will generate an interrupt from the keyboard. It is assumed that
the keyboard row lines are connected into Port A.
2
DRAMSZ: Determines width of DRAM memory interface, where:0 = 32-bit DRAM and 1 = 16-bit DRAM.
3
KBWEN: When the KBWEN bit is high, the EP7211 will get woken from a power saving state into the
Operating State when a high signal is on one of Port A’s inputs (irrespective of the state of the interrupt
mask register). This is called the Keyboard Direct Wakeup mode. In this mode, the interrupt request does
not have to get serviced. If the interrupt is masked (i.e., the interrupt mask register 2 (INTMR2) Bit 0 is
low), the processor simply starts re-executing code from where it left off before it entered the power saving
state. If the interrupt is non-masked, then the processor will service the interrupt.
4
SS2TXEN: Transmit enable for the synchronous serial interface 2. The transmit side of SSI2 will be dis-
abled until this bit is set. When set low, this bit also disables the SSICLK pin (to save power) in master
mode, if receive side is low.
7
SS2RXEN: Receive enable for the synchronous serial interface 2. The receive side of SSI2 will be dis-
abled until this bit is set. When both SSI2TXEN and SSI2RXEN are disabled, the SSI2 interface will be in
a power saving state.
88
Register Descriptions
DS352PP3
JUL 2001