EP7211 Datasheet, PDF (49/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 3-11. DRAM Address Mapping for a 16-Bit-Wide DRAM Memory System
EP7211 Size
4 Mbit
16 Mbit
16 Mbit
Address
Configuration
9 Row x 9 Column
10 Row x 10 Column
12 Row x 8 Column
Total Size of
Bank
0.5 Mbyte
2 Mbytes
2 Mbytes
64 Mbit
64 Mbit
11 Row x 11 Column
13 Row x 9 Column
8 Mbytes
8 Mbytes
256 Mbit
1 Gbit
12 Row x 12 Column
13 Row x 13 Column
32 Mbytes
128 Mbytes
Address Range of
Segment(s)
n000.0000–n007.FFFF
n000.0000–n01F.FFFF
n000.0000–n003.FFFF
n008.0000–n00B.FFFF
n020.0000–n023.FFFF
n028.0000–n02B.FFFF
n080.0000–n083.FFFF
n088.0000–n08B.FFFF
n0A0.0000–n0A3.FFFF
n0A8.0000–n0AB.FFFF
n000.0000–n07F.FFFF
n000.0000–n00F.FFFF
n020.0000–n02F.FFFF
n080.0000–n08F.FFFF
n0A0.0000–n0AF.FFFF
n200.0000–n20F.FFFF
n220.0000–n22F.FFFF
n280.0000–n28F.FFFF
n2A0.0000–n2AF.FFFF
n000.0000–n1FF.FFFF
n000.0000–n7FF.FFFF
Size of
Segment(s)
0.5 MByte
2 Mbytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
256 KBytes
8 Mbytes
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
32 Mbytes
128 Mbytes
The DRAM controller contains a programmable refresh counter. The refresh rate is controlled using
the DRAM refresh period register (DRFPR).
The 16/32-bit DRAM selection is made based on Bit 2 of the SYSCON2 register. Both banks must
have the same width.
SYSCON2 0x8000 1100 Bit 2 (DRAMSZ)0 = 32-bit DRAM
1 = 16-bit DRAM
The default is 32-bit width, since the SYSCON2 register is reset to all zeros on power-up.
DS352PP3
JUL 2001
49
Functional Description