EP7211 Datasheet, PDF (38/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Interrupt
IRQ
IRQ
IRQ
IRQ
Table 3-1. Interrupt Allocation in First Interrupt Register (cont.)
Bit in INTMR1
and INTSR1
12
13
14
15
Name
UTXINT1
URXINT1
UMSINT
SSEOTI
Comment
Internal UART1 transmit FIFO empty interrupt
Internal UART1 receive FIFO full interrupt
Internal UART1 modem status changed interrupt
Synchronous serial interface 1 end of transfer interrupt
Interrupt
IRQ
IRQ
IRQ
IRQ
IRQ
Table 3-2. Interrupt Allocation in Second Interrupt Register
Bit in INTMR2
and INTSR2
0
1
2
12
13
Name
KBDINT
SS2RX
SS2TX
UTXINT2
URXINT2
Comment
Key press interrupt
Master/slave SSI 16 bytes received
Master/slave SSI 16 bytes transmitted
UART2 transmit FIFO empty interrupt
UART2 receive FIFO full interrupt
Interrupt
FIQ
Table 3-3. Interrupt Allocation in Third Interrupt Register
Bit in INTMR3
and INTSR3
0
Name
MCPINT
MCP interface interrupt
Comment
3.3.1 Interrupt Latencies in Different States
3.3.1.1 Operating State
The ARM720T processor checks for a low level on its FIQ/IRQ inputs at the end of each instruction.
First, there is a one to two clock cycle synchronization penalty. For the case where the EP7211 is
operating at 13 MHz with a 16-bit external memory system, and instruction sequence stored in one
wait state Flash memory, the worst case interrupt latency is 251 clock cycles. This corresponds to the
processor executing a STM instruction to DRAM, and where the MMU needs to fetch protection/
translation information from page tables in DRAM memory. This includes a delay for cache line fills
for instruction prefetches, and a data abort occurring at the end of the LDM instruction, and the LDM
being non-quad word aligned. In addition, the worst-case interrupt latency assumes that LCD DMA
cycles to support a panel size of 320 x 240 at 4 bits-per-pixel, 60 Hz refresh rate, is in progress.
38
Functional Description
DS352PP3
JUL 2001