EP7211 Datasheet, PDF (80/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5. REGISTER DESCRIPTIONS
5.1 Internal Registers
Table 5-1. Internal I/O Memory Locations shows all internal registers in the EP7211, assuming
the CPU is configured for operation with a Little Endian memory system. Table 5-2.Port Byte
Addresses in Big Endian Mode shows the differences that occur for byte-wide access to Ports A,
B, and D with the CPU configured to operate in the Big Endian mode. All the internal registers are
inherently Little Endian (i.e., the least significant byte is attached to bits 7 to 0 of the data bus).
Hence, the system Endianness affects the addresses required for byte accesses to the internal
registers, resulting in a reversal of the byte address required to read/write a particular byte within a
register. Note that the internal registers have been split into two groups – the “old” and the “new”.
The old ones are the same as that used in CL-PS7111 and are there for compatibility. The new
registers are for accessing the additional functionality of the MCP interface and the LED flasher.
There is no effect on the register addresses for word accesses. Bits A0 and A1 of the internal address
bus are only decoded for Ports A, B, and D (to allow read/write to individual ports). For all other
registers, bits A0 and A1 are not decoded, so that byte reads will return the whole register contents
onto the EP7211’s internal bus, from where the appropriate byte (according to the Endianness) will
be read by the CPU. For example, to read data back from the DRAM refresh period register (which
is only 8 bits wide) requires address 0x80000200 if read as a word (irrespective of Endianness), or
as a byte in the Little Endian mode, but a byte read to obtain the register contents in Big Endian mode
must output address 0x80000203. To avoid the additional complexity, it is preferable to perform all
internal register accesses as word operations, except for ports A to D which are explicitly designed
to operate with byte accesses, as well as word accesses.
An 8K segment of memory in the range 0x8000.0000 to 0x8000.3FFF is reserved for internal use in
the EP7211. Accesses in this range will not cause any external bus activity unless debug mode is
enabled. Writes to bits that are not explicitly defined in the internal area are legal and will have no
effect. Reads from bits not explicitly defined in the internal area are legal but will read undefined
values. All the internal addresses should only be accessed as 32-bit words and are always on a word
boundary, except for the PIO port registers, which can be accessed as bytes. Address bits in the range
A0 –A5 are not decoded (except for Ports A–D), this means each internal register is valid for 64 bytes
(i.e., the SYSFLG1 register appears at locations 0x8000.0140 to 0x8000.017C). There are some gaps
in the register map for backward compatibility reasons, but registers located next to a gap are still
only decoded for 64 bytes.
The GPIO port registers are byte-wide and can be accessed as a word but not as a half-word. These
registers additionally decode A0 and A1. All addresses are in hexadecimal notation.
NOTE: All byte-wide registers should be accessed as words (except Port A to Port D registers, which are
designed to work in both word and byte modes).
All registers bit alignment starts from the LSB of the register (i.e., they are all right shift justified).
The registers which interact with the 32 kHz clock or which could change during readback (e.g., RTC
data registers, SYSFLG register (lower 6-bits only), the TC1 and 2 data registers, port registers, inter-
80
Register Descriptions
DS352PP3
JUL 2001