EP7211 Datasheet, PDF (39/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
This would give a worst-case interrupt latency of about 19.3 µs for the ARM720T processor
operating at 13 MHz in this system. For those interrupt inputs which have de-glitching, this figure is
increased by the maximum time required to pass through the deglitcher, which is approximately 61
µs (1 cycle of the 16.384 kHz clock derived from the RTC oscillator). This would create an absolute
worst case latency of approximately 80 µs. If the ARM720T is run at 36 MHz or greater and/or 32-
bit wide external memory, the 19.3 µs value will be reduced.
All the serial data transfer peripherals included in the EP7211 (except for the master-only SSI1) have
local buffering to ensure a reasonable interrupt latency response requirement for the OS of 1 ms or
less. This assumes that the maximum data rates described in this specification are complied with. If
the OS cannot meet this requirement, there will be a risk of data over/underflow occurring.
3.3.1.2 Idle State
When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after approximately
two clock cycles. However, there is still potentially up to 20 µs latency as described in the first
section above, unless the code is written to include at least two single cycle instructions immediately
after the write to the IDLE register (in which case the latency drops to a few microseconds). This is
important, as normally the Idle State will have been left because of a pending interrupt, which has to
be synchronized by the processor before it can be serviced.
3.3.1.3 Standby State
In the Standby State, the latency will depend on whether the system clock is shut down and if the
FASTWAKE bit in the SYSCON3 register is set. If the system is configured to run from the internal
PLL clock, then the PLL will always be shut down when in the Standby State. In this case, if the
FASTWAKE bit is cleared, then there will be a latency of between 0.125 s to 0.25 s. If the
FASTWAKE bit is set, then there will be a latency of between 250 µs to 500 µs. If the system is
running from the external clock (at 13 MHz), with the CLKENSL bit in SYSCON2 set to 0, then the
latency will also be between 0.125 s and 0.25 s to enable an external oscillator to stabilize. In the case
of a 13 MHz system where the clock is not disabled during the Standby State (CLKENSL = 1), then
the latency will be the same as described in the Idle State section above.
Whenever the EP7211 is in the Standby State, the external address and data buses are driven low.
The RUN signal is used internally to force these buses to be driven low. This is done to prevent
peripherals that are power-down from draining current. Also, the internal peripheral’s signals get set
to their Reset State.
DS352PP3
JUL 2001
39
Functional Description