EP7211 Datasheet, PDF (128/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
This process is repeated for each new piece of data received until at least one empty FIFO entry
exists. When the TRO bit is set, an interrupt request is made.
5.16.3.9 Audio Transmit FIFO Not Full Flag (ANF) (read-only, non-interruptible)
The audio transmit FIFO not full flag (ANF) is a read-only bit which is set whenever the audio
transmit FIFO contains one or more entries which do not contain valid data and is cleared when the
FIFO is completely full. This bit can be polled when using programmed I/O to fill the audio transmit
FIFO. This bit does not request an interrupt.
5.16.3.10 Audio Receive FIFO Not Empty Flag (ANE) (read-only, non-interruptible)
The audio receive FIFO not empty flag (ANE) is a read-only bit which is set when ever the audio
receive FIFO contains one or more entries of valid data and is cleared when it no longer contains any
valid data. This bit can be polled when using programmed I/O to remove remaining data from the
receive FIFO. This bit does not request an interrupt.
5.16.3.11 Telecom Transmit FIFO Not Full Flag (TNF) (read-only, non-interruptible)
The telecom transmit FIFO not full flag (TNF) is a read-only bit which is set when ever the telecom
transmit FIFO contains one or more entries which do not contain valid data. It is cleared when the
FIFO is completely full. This bit can be polled when using programmed I/O to fill the telecom
transmit FIFO. This bit does not request an interrupt.
5.16.3.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only, non-interruptible)
The telecom receive FIFO not empty flag (TNE) is a read-only bit which is set when ever the telecom
receive FIFO contains one or more entries of valid data and is cleared when it no longer contains any
valid data. This bit can be polled when using programmed I/O to remove remaining data from the
receive FIFO. This bit does not request an interrupt.
5.16.3.13 Codec Write Completed Flag (CWC) (read-only, non-interruptible)
The codec write completed (CWC) flag is set after the following sequence occurs:
1) A register write command is issued to the codec by writing to MCDR2.
2) The write command is sent to the codec via subframe 0.
3) The data value is latched within the addressed codec register at the beginning of subframe 1 (the
65th bit of the frame).
4) The address and value which was written is returned to the MCP via the next subframe 0.
5) The returned value is latched in MCDR2.
CWC is automatically cleared when MCDR2 is read or written. This bit does not request an interrupt.
5.16.3.14 Codec Read Completed Flag (CRC) (read-only, non-interruptible)
The codec read completed (CRC) flag is set after the following sequence occurs:
128
Register Descriptions
DS352PP3
JUL 2001