EP7211 Datasheet, PDF (102/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
in the DRAM refresh period register is only cleared by a power-on reset (i.e., its state is maintained
during a power fail or user reset).
Bit
Description
7
RFSHEN: DRAM Refresh enable. Setting this bit enables periodic refresh cycles to be generated by the
EP7211 at a rate set by the RFDIV field. Setting this bit also enables self refresh mode when the EP7211
is in the Standby State.
0:6
RFDIV: This 7-bit field sets the DRAM refresh rate. The refresh period is derived from a
128 kHz clock and is given by the formula:
Frequency (kHz) = 128 / (RFDIV + 1)
i.e., RFDIV = (128 / Refresh frequency (kHz)) – 1
This equation is valid for both 13 MHz and 18.432–73.728 Mhz modes. The equation for frequency gives
the refresh rate for the DRAM.
The maximum refresh frequency is 64 kHz: the minimum is 1 kHz. The RFDIV field should not be pro-
grammed with zero as this will result in no refresh cycles being initiated. These values are valid for both 13
MHz and 18.432–73.728 MHz modes of operation.
5.5 Timer/Counter Registers
5.5.1 TC1D Timer Counter 1 Data Register
ADDRESS: 0x8000.0300
The timer counter 1 data register is a 16-bit read/write register which sets and reads data to TC1. Any
value written will be decremented on the next rising edge of the clock.
5.5.2 TC2D Timer Counter 2 Data Register
ADDRESS: 0x8000.0340
The timer counter 2 data register is a 16-bit read/write register which sets and reads data to TC2. Any
value written will be decremented on the next rising edge of the clock.
5.5.3 RTCDR Realtime Clock Data Register
ADDRESS: 0x8000.0380
The real time clock data register is a 32-bit read/write register, which sets and reads the binary time
in the RTC. Any value written will be incremented on the next rising edge of the 1 Hz clock. This
register is reset only by NPOR.
5.5.4 RTCMR Realtime Clock Match Register
ADDRESS: 0x8000.03C0
The Realtime Clock match register is a 32-bit read/write register, which sets and reads the binary
match time to RTC. Any value written will be compared to the current binary time in the RTC, if
they match it will assert the RTCMI interrupt source. This register is reset only by NPOR.
102
Register Descriptions
DS352PP3
JUL 2001