EP7211 Datasheet, PDF (15/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
2.2.1 External Signal Functions
Function
Data bus
Signal
Name
D[0–31]
A[0–14]
Address bus
A[15]/
DRA[12]–
A[27]/DRA[0]
NRAS[0–1]
NCAS[0–3]
NMOE
NMWE
NCS[0–3]
Memory and
Expansion
Interface
NCS[4–5]
EXPRDY
WRITE
WORD
HALFWORD
EXPCLK
Signal
Description
I/O
32-bit system data bus for DRAM, ROM/SRAM/Flash, and memory mapped
I/O expansion
O
Least significant 15 bits of system byte address during ROM/SRAM/Flash and
expansion cycles
O
13-bit multiplexed DRAM word address during DRAM cycles or address bits
16 to 27 of system byte address during ROM/SRAM/Flash and expansion
cycles
– Whenever the EP7211 is in the Standby State, the external address and
data buses are driven low. The RUN signal is used internally to force these
buses to be driven low. This is done to prevent peripherals that are power-
down from draining current. Also, the internal peripheral’s signals get set to
their Reset State.
– For additional power saving, the multiplexed DRAM address lines are output
on the high order ROM address lines where the lightest loading is expected.
O
DRAM RAS outputs to DRAM banks 0 to 1
I/O
DRAM CAS outputs for bytes 0 to 3 within 32-bit word
O
DRAM, ROM/SRAM/Flash, and expansion output enable
O
DRAM, ROM/SRAM/Flash, and expansion write enable
O
Expansion channel I/O strobes; active low SRAM-like chip selects for expan-
sion
O
Expansion channel I/O strobes; active low CS for expansion or for
CL-PS6700 select
I/O
Expansion channel ready; external expansion devices drive this low to extend
the bus cycle
O
Transfer direction, low during reads, high during writes from the
EP7211
O
Word access enable; driven high during word-wide cycles, low during byte-
wide cycles
O
Half-Word access flag; driven high to denote upper half-word accesses
I/O
Expansion clock rate is the same as the CPU clock for 13 MHz and 18 MHz. It
runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is
used as the clock input
DS352PP3
JUL 2001
15
Pin Information