EP7211 Datasheet, PDF (93/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.2.5 SYSFLG2 System Status Register 2
ADDRESS: 0x8000.1140
7
Reserved
6
CKMODE
5
SS2TXUF
4
SS2TXFF
3
SS2RXFE
2
RESFRM
1
RESVAL
0
SS2RXOF
15
Reserved
14
Reserved
13
Reserved
12
Reserved
11
UBUSY2
10
Reserved
9
Reserved
8
Reserved
23
UTXFF2
22
URXFE2
21:16
Reserved
This register is an extension of SYSFLG1, containing status bits for backward compatibility with
CL-PS7111. The bits of the second system status register are defined below.
Bit
11
22
23
3
5
4
0
1
2
6
Description
UBUSY2: UART2 transmitter busy. This bit is set while UART2 is busy transmitting data; it is guaranteed
to remain set until the complete byte has been sent, including all stop bits.
URXFE2: UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in
the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set when the RX holding
register contains is empty. If the FIFO is enabled the URXFE bit will be set when the RX FIFO is empty.
UTXFF2: UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in
the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set when the TX holding
register is full. If the FIFO is enabled the UTXFF bit will be set when the TX FIFO is full.
SS2RXFE: Master/slave SSI2 RX FIFO empty bit. This will be set if the 16 x 16 RX FIFO is empty.
SS2TXUF: Master/slave SSI2 TX FIFO Underflow bit. This will be set if there is attempt to transmit when
TX FIFO is empty. This will be cleared when FIFO gets loaded with data.
SS2TXFF: Master/slave SSI2 TX FIFO full bit. This will be set if the 16 x 16 TX FIFO is full. This will get
cleared when data is removed from the FIFO or the EP7211 is reset.
SS2RXOF: Master/slave SSI2 RX FIFO overflow. This bit is set when a write is attempted to a full RX FIFO
(i.e., when RX is still receiving data and the FIFO is full). This can be cleared in one of two ways:
1. Empty the FIFO (remove data from FIFO) and then write to SRXEOF location.
2. Disable the RX (affects of disabling the RX will not take place until a full SSI2 clock
cycle after it is disabled)
RESVAL: Master/slave SSI2 RX FIFO residual byte present, cleared by popping the residual byte into the
SSI2 RX FIFO or by a new RX frame sync pulse.
RESFRM: Master/slave SSI2 RX FIFO residual byte present, cleared only by a new RX frame sync pulse.
CKMODE: This bit reflects the status of the CLKSEL (Port E Bit 2) input, latched during NPOR. When low,
the PLL is running and the chip is operating in 18.432–73.728 MHz mode. When high the chip is operating
from an external 13 MHz clock.
DS352PP3
JUL 2001
93
Register Descriptions