EP7211 Datasheet, PDF (94/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.3 Interrupt Registers
5.3.1 INTSR1 Interrupt Status Register 1
ADDRESS: 0x8000.0240
7
EINT3
6
EINT2
5
EINT1
4
CSINT
3
MCINT
2
WEINT
1
BLINT
0
EXTFIQ
15
SSEOTI
14
UMSINT
13
URXINT1
12
UTXINT1
11
TINT
10
RTCMI
9
TC2OI
8
TC1OI
The interrupt status register is a 32-bit read only register. The interrupt status register reflects the
current state of the first 16 interrupt sources within the EP7211. Each bit is set if the appropriate
interrupt is active. The interrupt assignment is given below.
Bit
0
1
2
3
4
5
6
Description
EXTFIQ: External fast interrupt. This interrupt will be active if the NEXTFIQ input pin is forced low and is
mapped to the FIQ input on the ARM720T processor.
BLINT: Battery low interrupt. This interrupt will be active if no external supply is present (NEXTPWR is
high) and the battery OK input pin BATOK is forced low. This interrupt is de-glitched with a 16 kHz clock,
so it will only generate an interrupt if it is active for longer than
61 µs. It is mapped to the FIQ input on the ARM720T processor and is cleared by writing to the BLEOI
location.
NOTE: BLINT is disabled during the Standby State.
WEINT: Watch dog expired interrupt. This interrupt will become active on a rising edge of the periodic 64
Hz tick interrupt clock if the tick interrupt is still active (i.e., if a tick interrupt has not been serviced for a
complete tick period). It is mapped to the FIQ input on the ARM720T processor and the TEOI location
NOTE: WEINT is disabled during the Standby State.
Watch dog timer tick rate is 64 Hz (in 13 MHz and 73.728–18.432 MHz modes).
NOTE: Watchdog timer is turned off during the Standby State.
MCINT: Media changed interrupt. This interrupt will be active after a rising edge on the NMEDCHG input
pin has been detected, This input is de-glitched with a 16 kHz clock so it will only generate an interrupt if it
is active for longer than 61 µs. It is mapped to the FIQ input on the ARM7TDMI processor and is cleared
by writing to the MCEOI location. On power-up, the Media change pin (NMEDCHG) is used as an input to
force the processor to either boot from the internal Boot ROM, or from external memory. After power-up,
the pin can be used as a general purpose FIQ interrupt pin.
CSINT: Codec sound interrupt, generated when the data FIFO has reached half full or empty (depending
on the interface direction). It is cleared by writing to the COEOI location.
EINT1: External interrupt input 1. This interrupt will be active if the NEINT1 input is active (low) it is cleared
by returning NEINT1 to the passive (high) state.
EINT2: External interrupt input 2. This interrupt will be active if the NEINT2 input is active (low) it is cleared
by returning NEINT2 to the passive (high) state.
94
Register Descriptions
DS352PP3
JUL 2001