EP7211 Datasheet, PDF (91/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.2.4 SYSFLG — The System Status Flags Register
ADDRESS: 0x8000.0140
7:4
3
DID
WUON
2
WUDR
1
DCDET
0
MCDR
15
CLDFLG
14
PFFLG
13
RSTFLG
12
NBFLG
11
UBUSY1
10
DCD
9
DSR
8
CTS
23
UTXFF1
22
URXFE1
21:16
RTCDIV
31:30
VERID
29
28
27
26
25
24
ID
BOOTBIT1
BOOTBIT0
SSIBUSY
CTXFF
CRXFE
The system status flags register is a 32-bit read only register, which indicates various system
information. The bits in the system status flags register SYSFLG are defined in the following table.
Bit
0
1
2
3
4:7
8
9
10
11
12
13
Description
MCDR: Media changed direct read. This bit reflects the INVERTED non-latched status of the media
changed input.
DCDET: This bit will be set if a non-battery operated power supply is powering the system (it is the inverted
state of the NEXTPWR input pin).
WUDR: Wake up direct read. This bit reflects the non-latched state of the wakeup signal.
WUON: This bit will be set if the system has been brought out of the Standby State by a rising edge on the
wakeup signal. It is cleared by a system reset or by writing to the HALT or STDBY locations.
DID: Display ID nibble. This 4-bit nibble reflects the latched state of the four LCD data lines. The state of
the four LCD data lines is latched by the LCDEN bit, and so it will always reflect the last state of these lines
before the LCD controller was enabled. These bits identify the LCD display panel fitted.
CTS: This bit reflects the current status of the clear to send (CTS) modem control input to UART1.
DSR: This bit reflects the current status of the data set ready (DSR) modem control input to UART1.
DCD: This bit reflects the current status of the data carrier detect (DCD) modem control input to UART1.
UBUSY1: UART1 transmitter busy. This bit is set while UART1 is busy transmitting data, it is guaranteed
to remain set until the complete byte has been sent, including all stop bits.
NBFLG: New battery flag. This bit will be set if a low to high transition has occurred on the NBATCHG
input, it is cleared by writing to the STFCLR location.
RSTFLG: Reset flag. This bit will be set if the RESET button has been pressed, forcing the NURESET
input low. It is cleared by writing to the STFCLR location.
DS352PP3
JUL 2001
91
Register Descriptions