EP7211 Datasheet, PDF (62/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
NOTE: All the writes/reads to the FIFO are done word at a time (data on the lower 16 bits is valid and upper
16 bits are ignored)...
Residual bit valid
00
11
New RX byte received
New RX byte
received
01
Pop FIFO
Figure 3-8. Residual Byte Reading
Software manually pops the residual byte into the RX FIFO by writing to the SS2POP location (the
value written is ignored). This write will strobe the RX FIFO write signal, causing the residual byte
to be written into the FIFO.
3.8.4.2 Support for Asymmetric Traffic
The interface supports asymmetric traffic (i.e., unbalanced data flow). This is accomplished through
separate transmit and receive frame sync control lines. In operation, the receiving node receives a
byte of data on the eight clocks following the assertion of the receive frame sync control line. In a
similar fashion, the sending node can transmit a byte of data on the eight clocks following the
assertion of the transmit frame sync pulse. There is no correlation in the frequency of assertions of
the RX and TX frame sync control lines (SSITXFR and SSIRXFR). Hence, the RX path may bear
a greater data throughput than the TX path, or vice versa. Both directions, however, have an absolute
maximum data throughput rate determined by the maximum possible clock frequency, assuming that
the interrupt response of the target OS is sufficiently quick.
3.8.4.3 Continuous Data Transfer
Data bytes may be sent/received in a contiguous manner without interleaving clocks between bytes.
The frame sync control line(s) are eight clocks apart and aligned with the clock representing bit D0
of the preceding byte (i.e., one bit in advance of the MSB).
3.8.4.4 Discontinuous Clock
In order to save power during the idle times, the clock line is put into a static low state. The master
is responsible for putting the link into the Idle State. The Idle State will begin one clock, or more,
after the last byte transferred and will resume at least one clock prior to the first frame sync assertion.
To disable the clock, the TX section is turned off.
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Functional Description
DS352PP3
JUL 2001