EP7211 Datasheet, PDF (135/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 6-2. AC Timing Characteristics (cont.)
Symbol
Parameter
T25
Data valid to falling NMWE for non sequential access
only
T31
SSICLK period (slave mode)
T32
SSICLK high
T33
SSICLK low
T34
SSICLK rise/fall time
T35
SSICLK rising to RX and/or TX frame sync
T36
SSICLK rising edge to frame sync low
T37
SSICLK rising edge to TX data valid
T38
SSIRXDA data set-up time
T39
SSIRXDA data hold time
T40
SSITXFR and/or SSIRXFR period
13 MHz
Min
Max
5
—
0
512
925
1025
925
1025
7
528
448
80
30
40
750
18/36 MHz
Min
Max
5
—
0
512
925
1025
925
1025
7
528
448
80
30
40
750
Units
ns
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 6-3. Timing Characteristics
Symbol
t_NCSRD
t_NCSWR
t_EXBST
t_RC
t_RAC
t_RP
t_CAS
t_CP
t_PC
t_CSR
t_RAS
Characteristics
Negative strobe (NCS[0–5]) zero wait
state read access time
Negative strobe (NCS[0–5]) zero wait
state write access time
Sequential expansion burst mode
read access time
DRAM cycle time
Access time from RAS
RAS precharge time
CAS pulse width
CAS precharge in page mode
Page mode cycle time
CAS set-up time for auto refresh
RAS pulse width
13 MHz
Min Max
120
120
55
230 —
110 —
110 —
30
—
20
—
70
—
20
—
110 —
18 MHz
Min Max
70
70
35
150
—
70
—
70
—
20
—
12
—
45
—
15
—
80 *
—
36 MHz
Min Max
50
50
8
150
50
50
10
10
20
5
50*
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS352PP3
JUL 2001
135
Electrical Specifications