EP7211 Datasheet, PDF (81/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
rupt status registers) should be read twice and compared to ensure that a stable value has been read
back.
Address
0x8000.0000
0x8000.0001
0x8000.0002
0x8000.0003
0x8000.0040
0x8000.0041
0x8000.0042
0x8000.0043
0x8000.0080
0x8000.00C0
0x8000.0100
0x8000.0140
0x8000.0180
0x8000.01C0
0x8000.0200
0x8000.0240
0x8000.0280
0x8000.02C0
0x8000.0300
0x8000.0340
0x8000.0380
0x8000.03C0
0x8000.0400
0x8000.0440
0x8000.0480
0x8000.04C0
0x8000.0500
0x8000.0540
Name
PADR
PBDR
—
PDDR
PADDR
PBDDR
—
PDDDR
PEDR
PEDDR
SYSCON1
SYSFLG
MEMCFG1
MEMCFG2
DRFPR
INTSR1
INTMR1
LCDCON
TC1D
TC2D
RTCDR
RTCMR
PMPCON
CODR
UARTDR1
UBLCR1
SYNCIO
PALMSW
Table 5-1. CL-PS7111-Compatible
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
0
0
0
0
0
0
RD/WR
RW
RW
—
RW
RW
RW
—
RW
RW
RW
RW
RD
RW
RW
RW
RD
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Size
8
8
8
8
8
8
8
8
3
3
32
32
32
32
8
32
32
32
16
16
32
32
12
8
8W/11R
32
32
32
Comments
Port A data register
Port B data register
Reserved
Port D data register
Port A data direction register
Port B data direction register
Reserved
Port D data direction register
Port E data register
Port E data direction register
System control register 1
System status flags register 1
Expansion and ROM memory configuration reg-
ister 1
Expansion and ROM memory configuration reg-
ister 2
DRAM refresh period register
Interrupt status register 1
Interrupt mask register 1
LCD control register
Read/Write data to TC1
Read/Write data to TC2
Realtime clock data register
Realtime clock match register
PWM pump control register
CODEC data I/O register
UART1 FIFO data register
UART1 bit rate and line control register
Synchronous serial I/O data register for master
only SSI
Least significant 32-bit word of LCD palette reg-
ister
DS352PP3
JUL 2001
81
Register Descriptions