EP7211 Datasheet, PDF (58/166 Pages) Cirrus Logic – HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
FIFOs. The user must ignore the non-significant bits. Figure 3-6. Format for the Audio and
Telecom FIFOs shows the required data alignment in the for the transmit and receive audio and
telecom FIFOs.
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Audio Data
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Telecom Data
Figure 3-6. Format for the Audio and Telecom FIFOs
3.8.2.5 MCP Codec Control Register Data Transfer
The UCB1100 contains sixteen 16-bit registers used to configure the chip, store touch-screen and
ADC samples, as well as digital I/O pin state and edge interrupt status. These registers are read and
written via the MCP’s serial interface using three fields of the MCP’s data frame. Referring to
Table 3-3, bits 15:0 contain the codec register value read from or written to the off-chip codec, bits
46:43 contain the register address of the current read or write, and Bit 42 is used by the MCP to
indicate a read or write cycle to the codec. These fields are configured by the CPU by writing to MCP
Data Register 2 and are then transmitted to the off-chip codec. These fields are also received in every
data frame, transmitted to the MCP from the codec, and are placed in MCP Data Register 2
(MCDR2), which in turn can be read by the CPU. Note that the contents of the addressed register,
which are sent along with the rest of the frame data to the codec, are returned in the receive data frame
regardless of the state of the read/write bit. Thus for write cycles, both a write and a read occurs, and
for read cycles, only a read occurs.
A codec register write is performed by writing a value to the MCDR2, or Frame Control Data
Receive/Transmit Register, which contains the value to store to the codec register, the address of the
codec register, and the read/write bit set to one. Once this register is written, its contents are
transferred to the correct fields within the serial shifter on the next rising-edge of the SIBSYNC
signal. The register information is transmitted to the UCB1100 during subframe 0, and the value is
written to the selected codec register at the end of subframe 0 (during the 65th bit of the frame). The
control register value and address are also returned to the MCP and stored in MCDR2. Typically, the
read/write bit is zero in the return frame. Because the addressed register is updated at the end of
subframe 0, the data returned during the frame in which the write occurred represents the previous
contents of the register. The updated value is returned during the next data frame.
A register read is performed by writing a value to MCDR2 which contains the address of the register
and the read/write bit set to a zero. Again, the data is transferred to the serial shifter on the next rising-
edge of the SIBSYNC signal and is transmitted to the UCB1100 during subframe 0. Because the
address and read/write control bit fields occur near the beginning of the serial stream output (or, in
other words, towards the end of the subframe — Bit 63), the codec performs the read immediately
58
Functional Description
DS352PP3
JUL 2001