Z80382 Datasheet, PDF (8/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
DC CHARACTERISTICS (Continued)
Specifications apply over Standard Operating Conditions unless otherwise noted.
Table 1. Output Class Characteristics
Output Class⁽¹⁾
Type
V_OL Max.
V_OH Min.
C_OUT Max.⁽²⁾
O
Totem Pole
0.4V @ I_OL = 2.0 ma
V_DD - 1.2V @ I_OH = 200 mA
15 pF
Slew Rate = 0.33 V/ns min @ C_LOAD = 50 pF
3
Tri-State
0.4V @ I_OL = 2.0 ma
V_DD - 1.2V @ I_OH = 200 mA
Slew Rate = 0.33 V/ns min @ C_LOAD = 50 pF
H
High Drive
0.4V max @ I_OL = 16 mA,
2.4V min @ I_OH = 5mA,
15 pF
Tri-State
V_DD = 5V
V_DD = 5V
Slew Rate = 0.33 V/ns min @ C_LOAD = 50 pF
D
Open-Drain
0.4V max @ I_OL = 16 mA
--
15 pF
Notes:
1. The Pin Numbers and Input/Output Classifications table in the previous section identifies the specific output pins in each
class.
2. Applies to Output only or I/O.
Table 2. Input Class Characteristics
Input Class⁽¹⁾
I
V_IL Max.
(Z80382)
0.8V
V_IL Max.
(Z8L382)
V_IH Min.
(Z80382)
V_IH Min.
(Z8L382)
0.6V
2.0V
2.0V
I_I = ±10 mA max, V_I = 0 to 5V (includes leakage if I/O)
C_IN = 5 pF max (if input only, see output type if I/O)
Minimum
Hysteresis
0.4V
Note: Inputs of this type include a weak-latch circuit, except that a register bit can disable those for pins PB7-0.
R
0.4V
0.4V
V_DD - 0.6V
V_DD - 0.3V
I_I = ±10 mA max, V_I = 0 to 5V
C_IN = 5 pF max
0.4V
Note: Inputs of this type except CLKI include a weak-latch circuit.
Notes:
1. The Pin Numbers and Input/Output Classifications table in the previous section identifies the specific input pins in each class.
8
PRELIMINARY
DS97Z382000