Z80382 Datasheet, PDF (56/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
SERIAL COMMUNICATION CHANNELS (Continued)
Baud Rate Generator and DPLL
If an HDLC channelÕs Tx clock is taken from its Baud Rate
Generator (BRG), and/or its Rx clock is taken from its
DPLL, then the channelÕs BRG operates. A BRG counts
down from the 16-bit value programmed into its Time Con-
stant LS and MS registers, using the processorÕs BUS-
CLK. Each time the value is zero, the BRG toggles its out-
put to the DPLL, and one clock later it reloads the value
from the Time Constant registers.
If an HDLC channelÕs Rx clocking is taken from its DPLL,
software should program the channelÕs Time Constant
registers with a 16-bit value that corresponds to 16 times
the nominal data rate. Conceptually, when the DPLL de-
tects a change on the raw Rx Data (before NRZI decod-
ing), it clears a counter that is incremented at 16X the nom-
inal bit rate. Half a bit time thereafter, it provides an active
edge on its Rx clock output. Thereafter, in the absence of
further data transitions it provides the Rx clock as the BRG
output divided by 16.
Per-Channel Registers
Each HDLC channel includes the following I/O-mapped
registers that can be read and written by the 380C proces-
sor:
s Transmit Mode Register
s Transmit Control/Status Register
s Transmit Interrupt Register
s Transmit Fill Register
s Receive Mode Register
s Receive Interrupt Register
s DMA Select Register
s Counter Access Port
Transmit Mode Register. Selects the main operating
mode of the Transmitter (transparent, HDLC, NRZI
HDLC), its I/O configuration (TDM, I/O by means of device
pins, and so on), when DMA data transfers are requested,
and action to be taken if an underrun occurs.
Transmit Interrupt Register. Controls and provides sta-
tus of potential interrupting conditions in the transmitter. It
also provides the mechanism for clearing conditions which
are causing an interrupt.
Transmit Fill Register. Holds a character that can be sent
between frames in HDLC mode, or in case of an Underrun
in Transparent mode.
Receive Mode Register. Selects the main operating
mode of the Receiver (transparent, HDLC, NRZI HDLC),
its I/O configuration (TDM, I/O by means of device pins,
and so on), when DMA data transfers are requested, when
the receiver begins assembling characters when it is
switched from the inactive state to transparent mode, and
the type of CRC used in HDLC modes.
Receive Interrupt Register. Most of the interrupt require-
ments for HDLC reception can be handled by enabling
Status interrupts in the DMA channel associated with each
Receiver. The only Receiver interrupt condition that is not
handled by this means is the Idle condition. Idle interrupts
are controlled by this register. This register also allows
several commands which deal with interrupts and Hunt
mode to be issued to the receiver.
DMA Select Register. Selects the DMA channels to be
used by the receiver and transmitter and enables their op-
eration.
Counter Access Port. Allows the 380C to write and read
the starting values for various counters in the HDLC chan-
nel. These are the Baud Rate Generator time constant, the
Transmitter TDM start and length values, and the Receiver
TDM start and length values.
Global HDLC Vector Register
This register provides the base interrupt vector for the
HDLC channels and identifies the HDLC device which is
causing an interrupt to be issued.
Tx Control/Status Register. Controls the minimum num-
ber of bits sent between frames and the minimum number
of bits sent after the Transmitter is enabled before the first
data character of a frame is sent, what the Transmitter
sends between frames, and the type of CRC used. It also
provides feedback on the current state of the transmitter.
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PRELIMINARY
DS97Z382000