Z80382 Datasheet, PDF (47/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
DMA CHANNELS
The DMA channels of the Z382 build on ZilogÕs experience proceeds to fetch the first Òlist entryÓ from memory, begin-
with the Z16C32 IUSC. They have only one mode of oper- ning at the address in the LAR.
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ation, which combines features of the IUSCÕs Array and
Linked List modes. Each DMA channel has a pointer into ^{List entries always begin at an 8-byte boundary, that is, at}
a list structure, entries in which contain the addresses and ^{an address having its LS three bits Ô000Õ. The general for-}
lengths of data buffers.
mat of a list entry includes eight bytes:
Since the on-chip peripherals of the Z382 all operate with
8-bit data only, particularly the HDLC channels which the
DMA channels are primarily intended to serve, the DMA
channels also perform only 8-bit data transfers when oper-
ating with data buffers. However, because fetching a new
list entry is an overhead operation that can compromise
maximum data rates, list accesses use 16-bit transfers.
DMA Channel/Device Interface
The interface between the DMA channel and its client de-
vice includes six lines:
Data Request
Terminate
Type Fetch
Data Acknowledge
End of Buffer
Store Status
Device to DMA
Device to DMA
DMA to device
DMA to device
DMA to device
DMA to device
All of these lines are bused, and are driven by the DMA
channel and its client device that are currently selected by
the DMA scanner.
Operation
A DMA channel starts operating when software loads an
address into its List Address Register (LAR). Writing the fi-
nal (MS) byte of this register sets the channelÕs Run bit,
which makes it request bus access from the processor.
When the processor grants bus access, the DMA channel
Address 7-0
Address 15-8
Address 23-16
should be 00
Type/Status
should be 00
Length 7-0
Length 15-8
Address of Byte
[LAR23-3] + 000
[LAR23-3] + 001
[LAR23-3] + 010
[LAR23-3] + 011
[LAR23-3] + 100
[LAR23-3] + 101
[LAR23-3] + 110
[LAR23-3] + 111
Figure 29. General Format of a DMA List Entry
The Type/Status byte defines various kinds of list entries,
as follows:
00
01
02
03
04
05
40-7F
80-BF
C0-FF
End of List
Transfer in List
Ready Buffer, no Command, no End of
Buffer notiÞcation
Ready Buffer, no Command, notify device at
End of Buffer
Buffer in Progress
Completed Buffer (no Status)
Ready Buffer, with Command, no End of
Buffer notiÞcation
Ready Buffer, with Command, notify device
at End of Buffer
Completed Buffer (with Status)
DS97Z382000
PRELIMINARY
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