Z80382 Datasheet, PDF (23/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
HDLC Receive Timing- Full Time HDLC Mode (See Figures 17 and 18)
Specifications apply over Standard Operating Conditions unless otherwise noted. C_L = 50 pF for outputs.
Z80382
Z8L382
1
No
Parameter
Min.
Max.
Min.
Max. Units Notes
t103 External Receive Clock Period
50
50
ns
1
t104 External Receive Clock Low Time
15
15
ns
t105 External Receive Clock High Time
15
15
ns
t106 External Receive Clock Rise Time
5
10
ns
t107 External Receive Clock Fall Time
5
10
ns
t108 RxD Setup to RxC Edge (External RxC)
20
20
ns
1
t109 RxD Hold from RxC Low/High (External
5
RxC)
5
ns
1
t110 RxC rise/fall time (Internal RxC)
5
10
ns
1
t111 RxD Setup to RxC Edge (Internal RxC)
20
25
ns
1
t112 RxD Hold from RxC Low/High (Internal
5
RxC)
10
ns
1
Note: 1. Receive clock sampling edge is configurable by means of RIRn[6]. See Z80382 User Manual.
RxC⁽¹⁾
(input)
RxD
t103
t104
t105
t106
t107
t109
t108
Note 1. HDLC clock triggering polarity is configurable by means of RIRn[6]. See Z80382 User Manual.
Figure 17. HDLC Receive Timing (Full Time HDLC, RxC Input)
DS97Z382000
PRELIMINARY
23