Z80382 Datasheet, PDF (34/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
PIN FUNCTIONS (Continued)
Pin Name
HA9-0
HD7-0
/PCIORD
/PCIOWR
/PCWE
/PCOE
/PCCE1
/PCREG
/INPACK
/PCIRQ
PCRESET
STSCHG
Table 9. PCMCIA Interface Signals
Pin
Number(s)
Description
66 - 67
69 - 76
78 - 85
61
60
89
90
91
63
62
87
92
88
PCMCIA Address Bus (inputs): Provide Host PC addressing of attribute memory, config-
uration registers, and Mimic. Decoded by the I/O address decoder.
PCMCIA Data Bus (input/outputs): Used for data transfers between the Host PC and the
Mimic, the attribute memory, and the configuration registers.
PCMCIA I/O Read (input, active Low): Used to generate the INPACK signal when an I/O
read cycle is within the configured range, and reads from the Mimic.
PCMCIA I/O Write (input, active Low): This signal is used to write to the Mimic.
PCMCIA Write Enable (input, active Low): Used to write to the attribute memory or to the
configuration register which is addressed by means of HA9-1. Such an operation is recog-
nized when /PCWE, /PCCE1, and /PCREG are all Low, and either the interface is config-
ured for ÒI/O and memoryÓ operation, or /PCIRQ is High, signifying ÒreadyÓ, when config-
ured as a Òmemory onlyÓ interface. The data applied while /PCWE is Low are written to the
attribute memory range on the positive edge of the /PCWE or Card-enable (/PCCE1) sig-
nal.
PCMCIA Output Enable (input, active Low): /PCOE, /PCCE1, and /PCREG all Low signify
a read from attribute memory or a configuration register as selected by HA9-1.
PCMCIA Chip Enable 1 (input, active Low): /PCCE1 Low indicates a read or write access
to: an even addressed byte in attribute memory, a configuration register, or the Mimic.
PCMCIA Register Select (input, active Low): /PCREG Low indicates a read or write ac-
cess to the attribute memory range or to the I/O address range.
PCMCIA Input Acknowledge (Output, active Low): /INPACK goes Low while an I/O read
access is performed within the configured I/O address range. If the PCMCIA interface is
configured such that it reacts independent of the address to all I/O read cycles, then /IN-
PACK is activated with /PCIORD.
PCMCIA Interrupt Request (Output, active Low): After the PCMCIA interface is reset it is
in a Òmemory-onlyÓ mode, and this signal is driven Low to signify a Busy state until the
380C writes a register bit to say it is Ready. After the card is then configured by the Host,
/PCIRQ goes Low to request a Host PC interrupt when the internal INT0 signal is asserted
by the Mimic. /PCIRQ is monitored by the PCMCIA Host adapter and, dependent on the
configuration, connected to one of the Host interrupts (for example, COM1 or COM2 inter-
rupt). /PCIRQ can be programmed to be a pulsed interrupt with a minimal pulse length of
one microsecond, or a level-interrupt that is reset when the interrupt is processed by the
Host. This choice is made by means of bit 6 of the Configuration Option Register.
PCMCIA Reset (input, active High): Setting PCRESET High resets the PCMCIA interface.
The card configuration register is cleared and the PCMCIA interface operates in the Òmem-
ory-onlyÓ mode until it is configured again. The attribute memory has to be initialized by the
controller, and the Ready/Busy (/PCIRQ) signal has to be deactivated.
PCMCIA Status Change (output): This output is controlled by a bit in the PCMCIA mod-
uleÕs 380C Control Register.
34
PRELIMINARY
DS97Z382000