Z80382 Datasheet, PDF (2/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
GENERAL DESCRIPTION (Continued)
Other additions to the instruction set include a full comple-
ment of 16-bit arithmetic and logical operations, 16-bit I/O
operations, multiply and divide, and a complete set of reg-
ister-to-register loads and exchanges.
The 380C register file includes alternate versions of the IX
and IY registers. There are four banks of registers in the
380C, along with instructions for switching among them.
All of the 16-bit register pairs and index registers in the ba-
sic Z80 microprocessor register file are expanded to 32
bits.
The Z382 includes dynamic bus sizing to allow any mix of
16- and 8-bit memory, and I/O devices in a system. One
application for this capability would be to copy code from a
low-cost, slow 8-bit ROM to 16-bit RAM, from which it can
be executed at much higher speeds. Memory bus sizes
can be configured internally by software to eliminate the
need for external logic to drive MSIZE.
Some features that have traditionally been handled by ex-
ternal peripherals have been incorporated in the Z382.
These on-chip peripherals reduce system chip count and
interconnections on the external bus. These peripherals, il-
lustrated in the Z382 Block Diagram in Figure 1, are sum-
marized below.
HDLC Synchronous Channels. Three HDLC channels
operate at serial data rates of up to 10 Mbps and feature
8-byte receive and transmit FIFOs. These can be used for
modems, general data communications, and ISDN. The
ISDN can be handled separately or through the GCI/SCIT
bus interface. HDLC Channels always transfer data
through the DMA channels. A transparent mode is select-
able. Two of the HDLC cells can be pin multiplexed with
the ASCIs (UARTs) to provide dynamically switchable
(async-sync) DTE interfaces.
DMA Channels. The eight DMA channels provide 24-bit
memory addressing and can transfer memory block sizes
of up to 64 KB (16-bits). These DMA channels can be dy-
namically assigned to serve the HDLC ports, Mimic COM
port, Host DMA Mailbox, or ASCIs in any mixture. Linked
list operation allows all HDLC transmitters and receivers to
operate at or above E1 rates simultaneously without load-
ing the bus bandwidth.
ASCI. Two flexible asynchronous serial channels with
baud rate generators, modem control and status.
CSIO. A clocked serial I/O channel which can be used for
serial memory interface.
Timers. Two 16-bit counter/timers with flexible prescalers
for wide-range timing applications.
GCI/SCIT Bus Interface. A common interface to ISDN in-
terface devices. Internal signals from this module can be
connected to the HDLC channels to provide B-channels
and D-channel for ISDN.
Plug-and-Play ISA Interface. Provides auto-configura-
tion in ISA (AT bus) applications.
PCMCIA Interface. Provides connectivity to a PCMCIA
bus.
32-Bit General-Purpose I/O. For non-PC add-in applica-
tions, four 8-bit ports are provided for general- purpose I/O.
In ISA or PCMCIA applications, the pins from two of the
ports are reallocated to host bus signals and are not avail-
able. Pins from the other two ports are selectively multi-
plexed with on-chip peripheral functions (ASCIs, CSI/O,
PRT). These pins are individually programmable for in-
put/output mode.
I/O Chip Selects. Two I/O chip selects are provided to
support I/O access of external peripherals. Each has a pro-
grammable base address and provides I/O decode sizes
ranging from 8 to 512 bytes.
ROM/RAM Chip Selects with Wait-State Generators.
Chip select outputs are provided to decode memory ad-
dresses and provide memory chip enables. Each chip se-
lect has its own Wait State Generator to allow use of mem-
ories with different speeds.
Watch-Dog Timer. A Watch-Dog Timer (WDT) with a wide
range of time-constants prevents code runaway and pos-
sible resulting system damage. The /RESET input can be
forced as an output upon the terminal count of the WDT.
This allows external peripherals to be reset along with the
Z382.
16550 Mimic. Provides connection to a PC ISA bus and
emulation of the 16550 UART register set. Improvements
include 16 mA output drivers and internal COM port ad-
dress decoding to reduce external PC interface compo-
nents.
2
PRELIMINARY
DS97Z382000