Z80382 Datasheet, PDF (57/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
GCI/SCIT Interface
Monitor Channels. There are two channels, monitor 0
GCI/SCIT Frame Structure (Terminal Mode)
GCI/SCIT includes three sub-frames called channels 0, 1,
and 2; each containing 32 bits. This 12-byte frame is re-
and monitor 1. Each channel consists of eight bits of data
and two associated handshake bits, MR and MX, that con-
trol data flow.
1
peated at a rate of 8 KHz, which gives an aggregate data
rate of 768 Kbits/second. The frame structure is shown in
Figure 36 below.
D Channel. The 16 Kbps D channel (2 bits per frame) pro-
vides a connection between the layer two and layer one
components.
B Channels. B1 and B2 are the first two 8-bit time slots af-
ter the frame sync pulse. Each B channel provides 64
Kbps of user data to/from the network.
FS
88
8 24
2
88
8
6
2
8882 4 2
DD B1 B2 MON0 D C/I0 MR-MX IC1 IC2 MON1 C/I1 MR-MX
C/I2
DU B1 B2 MON0 D C/I0 MR-MX IC1 IC2 MON1 C/I1 MR-MX
C/I2
GCI Channel 0
GCI Channel 1
GCI Channel 2
Figure 32. GCI/SCIT Frame Structure
Command/Indicate Channels. Three command/indicate
channels, C/I0, C/I1 and C/I2 are provided. Each sub-
frame has one. (C/I2 is the same as TIC, as indicated be-
low.) These channels provide real-time status between de-
vices connected by means of the GCI/SCIT bus.
Intercommunication Channels. Two intercommunica-
tion subchannels are provided in GCI channel 1. These
provide 64 Kbps data paths between user devices.
TIC Bus. This is the same as C/I2 and is used for D chan-
nel access with some GCI/SCIT devices. It allows multiple
layer-2 devices to individually gain access to the D and C/I
channels located in the first sub-frame.
The data signals on the GCI/SCIT bus are called Data Up-
stream (DU) and Data Downstream (DD). While each of
these is a bus that can be sensed as well as driven in an
open-drain (open-collector) fashion by the Z382 and other
devices, GCI practice defines certain fields on each line to
flow in certain directions.
The Z382 always receives from DD and (when enabled)
drives DU in the B2, MON0, D, C/I0, and MX0 fields. The
382 always receives from DU and (when enabled) drives
DD in the MR0 bit. Which line is driven and which is re-
ceived can be selected by software for the IC1, IC2,
MON1, and C/I1 fields and the MX1 and MR1 bits, with
MR1 always being in the opposite direction from MON1
and MX1.
Monitor Channel Operation
The monitor channels are full duplex and operate on a
pseudo-asynchronous basis, in other words, data trans-
fers take place synchronized to frame sync but the flow is
controlled by a handshake procedure using the MX and
MR bits. The handshake procedure (flow of events) is
shown in Figure 37 below.
Idle: The MX and MR pair being held inactive (High) for
two or more frames constitutes the channel being idle in
that direction. The data received in the monitor channel is
invalid and should be Ò11111111.Ó
DS97Z382000
PRELIMINARY
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