Z80382 Datasheet, PDF (62/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued)
counts down to 0, it is automatically reloaded with the val-
ue contained in its Timer Reload Register (RLDR).
Timer Reload Registers. Each PRT has a 16-bit Timer
Reload Register (RLDR) When a PRT channelÕs TMDR
counts down to 0, it is automatically reloaded with the con-
tents of its RLDR. Figure 40 below illustrates the operation
of the PRT.
Reset
Timer Data
Register
Timer Data Register
Write (0004H)
FFFFH 0004H
Timer Reload Register
Write (0003H)
0<t<f
f
f
f
f
f
f
f
f
f
0003H 0002H 0001H 0000H 0003H 0002H 0001H 0000H 0003H
Reload
Reload
Timer Reload
Register
FFFFH 0003H
Write Ò1Ó to TDE
Timer
Downcount
Enable
Timer
Interrupt
Flag
Note: f is BUSCLK divided by the value specified in TPR.
Timer Data Register Read
Timer Control Register Read
Figure 36. PRT Operation
62
PRELIMINARY
DS97Z382000