Z80382 Datasheet, PDF (49/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
If the device signalled Data Request, but not Terminate, _{Per-Channel Registers}
and the Buffer Length Register has now been counted
down to zero, the DMA channel proceeds as follows:
There are eight DMA channels in the Z382. Each channel
includes the following registers:
1
a. It puts the address of the Type/Status byte (from the
LAR) on the address bus, and writes the code for
ÒCompleted Buffer (no Status)Ó into that byte.
b. If the DMA channelÕs Buffer IE field indicates Òinterrupt
for all buffersÓ, or Òinterrupt for Notify buffersÓ and this
List Address Register
Buffer Address Register
Buffer Length Register
DMA Control/Status Register
(LAR, 21 bits)
(BAR, 24 bits)
(BLR, 16 bits)
(DCSR, 8 bits)
was a Notify buffer, it sets its IP bit to request an inter-
rupt.
The LAR and DCSR are read/write registers; software can
c. It increments the LAR to the address following this list
entry, and goes back to fetch a new list entry from that
address, as described above.
track the progress of a DMA by monitoring its LAR. BARs
and BLRs are accessible only by using special modes se-
lected in the centralized DMA Control Register; the chan-
nel stores ending BLR values in the list.
Terminate
The HDLC receiver asserts this signal for an End of
Frame, Abort, or Overrun condition. The HDLC Transmit-
ter does so for an Underrun condition. After the DMA chan-
nel transfers a byte, if the device signals Data Request and
Terminate, or if the device signals Terminate without Data
Request, the DMA channel proceeds as follows:
Note: If the device encounters an error from which
operation canÕt continue without processor attention, then
after signalling Terminate and storing a status byte as
described above, the device should refrain from asserting
Data Request until software has done so. (The HDLC
Transmitter does this for Underrun.)
a. It places the address of the Length field on the ad-
dress bus, and writes the current (16-bit) value in its
BLR to memory at that address and the next higher
address. This value enables software to tell how
much data was actually written into, or read out of,
this buffer.
b. It puts the address of the Type/Status byte on the ad-
dress bus, sets the control signals for a memory
write, signals ÒCompleted Buffer (with Status)Ó, and
asserts the Store Status signal to the device.
List Address Register
A three-byte register whose 21 most significant bits con-
tain the base address of the current list. The DMA channel
begins operation when the 380C writes the most signifi-
cant byte of this register. The DMA controller updates this
register as it processes new lists in response to links from
previous lists. The three LS bits of the LAR are ignored on
writing, and always read back as 100 (thus pointing at the
current Type/Status byte in the list).
Buffer Address Register
The DMA controller loads the initial value of the current
buffer address into this register from the address field of
the current list. At the end of each data transfer, the DMA
channel increments the BAR by one.
Buffer Length Register
The DMA controller loads the initial value of the current
buffer length into this register from the buffer length field of
the current list. At the end of each data transfer, the DMA
channel decrements the BLR by one.
c. In response to Store Status, the device can place up
to 6 bits of status on D5-0. For the HDLC receiver,
this status includes Overrun, End of Frame, Abort,
CRC Error, and the residual bit count. For the HDLC
Transmitter, only Underrun will prompt a Terminate
indication, so the specific status bits are unimportant.
d. 1. After the Type/Status byte has been written, the DMA
channel advances the LAR over this list entry, in other
words, to the address of the next entry.
e. If the DMA channelÕs Buffer IE field indicates any-
thing other than Óno buffer interruptsÓ, it requests an
interrupt.
f. The DMA channel then goes back to fetch another list
entry from the address in the LAR, as described
above.
DS97Z382000
PRELIMINARY
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